Training Course "SystemC-Basics, Modelling and Synthesis"

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 Training Course "SystemC-Basics, Modelling and Synthesis"

an ECSI Workshop

June 29, 2005
Paris, France



Workshop description

This course introduces into the system-level language SystemC. Special emphasis will be given on modelling across different levels of abstraction from untimed via timed transaction level models down to register transfer models including the needed refinement steps. Further topics are integration of hardware-dependent software and hardware synthesis from SystemC.


  • Introduction into the SystemC 2.1 language
  • Transaction-level modelling using SystemC

Tutor: Dr. Oliver Bringmann, FZI, Karlsruhe, Germany


Efficient Transaction Level Modelling

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Workshop description (PDF)

The workshop is intended to give an overview of the current status of the Transaction Level Modelling along four axes: efficient modelling techniques, industrial experiences, on-going standardisation activities and tool support.

Transaction Level Modelling concepts and techniques for abstract modelling are developed by several industrial users to cope basically with the simulation speed performance but also to enable early SW development in parallel to HW platform construction, design space exploration and also rapid development of verification reference models.

In addition, the coherent definition of higher abstraction levels, transaction and RT levels provide foundation for advanced techniques for mixed-level simulation (e.g. for IPs integration in SOC), formal verification, and synthesis or refinement flow.

The questions that can be raised are:

  • Do the existing tools support design methods and flows at TL? What breakthrough is expected by the users and how do the EDA companies plan to fulfil these needs?
  • What is the status on TLM standardisation. How the OSCI and SPIRIT standards will progress to be adopted, especially by IP suppliers, and finally successfully deployed across companies, beyond current company-internal successes?
  • How to best use jointly SystemC TLM with UML on one hand, and SystemC with SystemVerilog on the other hand?

Contributing companies:
STMicroelectronics, Bosch (TBC), Thales, Cadence, Synopsys, Summit Design, Prosilog, Celoxica, Silicomp, FZI, OFFIS

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