System Design Standards

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System Design Standards

an ECSI Workshop

December 16, 2003
Paris, France

Workshop description (PDF)



Successful system integration will rely on the use of applicable and efficient standards by the different partners involved in the system design process. An industry-wide synergy in the development, evaluation and adoption of these standards is required They will boost the capabilities of specification, verification and implementation methods combined and contribute to decrease the productivity gap of the design process of complex embedded systems.

This workshop is organised to update ECSI members or guests with the information about the emergence and evolution of some of the most important standards in system design domain: in system specification (UML, PSL), and in system design and implementation (SystemVerilog, SystemC, VHDL 200X, SystemC-AMS extension, OCP-IP standards).

The workshop sessions will encompass the current status of the standardisation process, future plans for standard evolution as well as technical introduction and overview of the standards. It will also bring an industry point of view on the requirements for standards in system design. The objective of this event is to present system level standardisation activities by ECSI members to other ECSI members. The information specifically related to standardisation process is presented under control of the appropriate standardisation bodies or working groups chairs.


1. The Unified Modelling Language: UML v2.0 and specialised profiles

  • Standard evolution at OMG - Francois Terrier, CEA
  • Technical presentation – Marko Boger, CEO, Gentleware

2. The Accellera standards: PSL and SystemVerilog

  • Accellera standardisation update - Dennis Brophy, Mentor Graphics - Accellera Chairman

3. Property Specification Language: PSL

  • PSL Syntax, PSL Tools, Discussion, IBM Perspective - Yaron Wolfsthal, IBM

4. System extensions to HDLs: SystemVerilog

  • Technical update - Peter Flake, Synopsys

5. The OSCI standard: SystemC

  • SystemC standardisation activities – Alain Clouard, ST Microelectronics
  • Technical update on SystemC (2.0.1) Axel Braun, ESCUG / University of Tübingen

6. SystemC/SystemVerilog relation
Markus Wloka, Director R&D, Synopsys Verification Group

7. System extensions to HDLs: IEEE/VHDL 200X
Gabriel Chidolue, Mentor Graphics UK

8. Open Core Protocol International Partnership
Ian Mackintosh, Sonics, Inc. – OCP IP President

9. System company requirements for industry standards in system design
Christophe Gendarme, Alcatel

10. Emerging candidate standard: SystemC-AMS
Alain Vachoux, EPFL

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