Keynotes

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Keynote 1:
IoT Trends and Innovative Applications

Speaker: Roberto Zafalon, STMicroelectronics, Italy

Abstract:
The keynote will tackle with the three major IoT challenges today: interoperability, security, and business model (monetization). The strong enabling technologies roots (i.e. semiconductor and IP Design) will set the stage for a comprehensive view of the key IoT end-markets and of the most innovative applications expected to boost the massive deployment of IoT by the next 4 years.

 
CV:
Dr. Roberto Zafalon is EU Technology Programmes Director - STMicroelectronics, Agrate Brianza (Milano), Italy, in charge to foster and leverage the link between ST technology groups and the R&D cooperative EU programs. In his current capacity since July 2007, he elaborates the vision and roadmap, seeks for project financing and drives industrial R&D teams to pursue innovative solutions in the field of IoT, embedded systems and nanolectronics, for corporate product divisions and labs. He is Steering Board member of ARTEMIS-IA and EPOSS and, as such, he is member of the ECSEL Governing Board.
He currently is, and has been in the past, General Project Manager and Coordinator of major Projects under FP6, FP7, ENIAC and ECSEL, including Large scale KET Pilot Lines. He has been selected by FP7-ICT, ARTEMIS JU, ECSEL and H2020 LEIT as independent expert to review the project submitted to some past calls.
From 2000 until June 2007, he has been the head of the Competence Center for Low Power System Design at the Advanced System Technology, the ST’s Corporate System R&D group. The main targets have been the next generation's embedded systems trade-offs, including algorithmic and architectural design exploration and power optimization, SW/HW partitioning and RF optimization and co-verification, power profiling, estimation and macro-modeling, energy efficient Network on Chip and RT-OS featuring dynamic power management policies.
As far as the on-chip communication is concerned, shared bus interconnects represent only a partial, short-term solution, because of their limited scalability. We focus on parallel and scalable interconnect architectures to support the rapidly growing communication bandwidth’s requirement, both in terms of Low Power Multi Processor Platforms and Energy Efficient NoC’s.
 
  

Keynote 2:
Programming in a Heterogeneous World

 

Speaker: Jan Kuper, QBayLogic, The Netherlands
 

Abstract:
Around 2005 the fast growth of the single core CPU was more or less over, after which both in industry and in academia a lot of effort was put into the development of alternative computing platforms, such as multi and many core archtectures, systems-on-chip, FPGAs and more course grain reconfigurable archtitectures, etcetera. However, programming many of these new platforms became a serious issue, and many attempts are undertaken to define translation mechansims from the well known and well developed programming methodology into often low-level platform specifc programming languages. As an example we just mention the existence of several high level synthesis tools for the specification of an FPGA, which translate among others C, C++, Java into VHDL or Verilog. However, none of these tools works really pleasantly.
In this talk we will argue that that the above described approach is doomed to fail because the way each type of computing platform deals with its internal space and time in a different way. Instead, we will argue that we should start from a really platform independent level, for which mathematics is a good candidate. It must be possible to develop compilers that translate - a subset of - mathematics into platform specifc languages. As an example will show the compiler CλaSH, which translates a close to mathematics specification into VHDL or Verilog for FPGA specification.

 

CV:
Jan Kuper studied logic and mathematics at the University of Twente, where he got his Master degree (with honours) in 1985. In 1994 he received his PhD degree under the supervision of Henk Barendregt on the foundations of mathematics and computer science. He developed a theory of partial functions and generalized to a theory of binary relations, which both are strong enough to be a foundation of mathematics.

He worked as a lecturer at the University of Leiden, as a researcher at the University of Nijmegen, and he now is an assistant professor at the university of Twente. His main fields of interest are philosophical and  mathematical logic, functional programming and hardware specification from a mathematical perspective. Based on the functional programming language Haskell he initiated the design of a mathematical language as a specification language for computer architectures (called CλaSH). Recently he co-founded QBayLogic, a company that designs FPGAs using CλaSH.

He published on the foundations of mathematics, lambda calculus, mathematical logic, specification languages for computer architectures, and on concrete FPGA designs.
 


  
Keynote 3:
Do  Design/Specification Languages have any role to play in Cyber-Security?

 

Speaker: Sandeep K. Shukla, India
 
Abstract:

Enterprise level cyber security is a nontrivial challenge for  chief information security officers (CISOs) as these systems are composed of  many subsystems with hierarchies of communication networks, interfaces with  the users of varying privileges, integration of distributed cyber assets and  information storage systems. This problem is further complicated in large  scale cyber physical critical infrastructure sectors due to the integration  of the physical dynamics, sensors/actuators, control and data acquisition  systems, and multiple layers of networks with varying degrees of openness.
 Attack surfaces are often hidden and in plenty,  unknown zero-day attacks  spring surprises, privileged users are often untrusted,  the failures of  components may suddenly open up new attack surfaces, and threat models are  often not formalized. A CISO is confronted with risk analysis, risk based  security budget apportioning, and introduce both attack prevention safe  guards (e.g firewalls, antivirus, software vulnerability scanners,  cryptographically secured booting, encrypted, and signed communications,  digital certificates, logging privileged users etc.), as well as continuous  surveillance to detect ongoing attacks. Is there a role for a  design/specification language in facilitating any of these? In this talk we  will explore this question, and we will show that there is indeed benefit in  taking approaches based on formalized languages for system specification, or  system design, not only for analyzability at various abstraction levels of  risk, and visibility  of attack vectors but also for better comprehension of  systemic risks, guiding resilient design of system architecture, and  budgeting resources in optimal manner. We will draw on examples of  meta-model driven languages, or extension of existing system modeling  languages to show the utility of formal specification languages and  frameworks to facilitate modeling, analysis and intervention.
 
 
CV:
Professor Sandeep K. Shukla is an IEEE fellow, an ACM Distinguished Scientist, and served as an IEEE Computer Society Distinguished Visitor during 2008-2012, and as an ACM Distinguished Speaker during 2007-2014. He is currently the Editor-in-Chief of ACM Transactions on Embedded Systems, and associate editor for ACM transactions on Cyber Physical Systems.  In the past, he has been associate editors for IEEE Transactions on Computers, IEEE Transactions on Industrial Informatics, IEEE Design & Test, IEEE Embedded Systems Letters, and many other journals. He has guest-edited more than 15 special issues for various IEEE and ACM journals. He has written or edited 9 books, published over 200 journal and conference papers. He has been program chairs for 4 IEEE/ACM International conferences, and General Chair for 2 of these conferences. He has served on the program committee of more than 100 international conferences and workshops. He supervised 12 PhDs, and directed five post-doctoral scholars at Virginia Tech.  Sandeep's current research focus is on Cyber Security for Critical Infrastructures. He is coordinating a research center on cyber security for critical infrastructures along with his colleagues at IIT Kanpur at the moment. He received his bachelor's degree in Computer Science and Engineering at Jadavpur University, Kolkata in 1991, his Masters and PhD degrees in Computer Science from the State University of New York at Albany, NY, USA in 1995 and 1997 respectively. He worked as a scientist at the GTE labs on telecommunications network management, distributed object technology, and event correlation technologies between 1997 and 1999. Between 1999 and 2001, he worked at the Intel Corporation on the formal verification of the ITANIUM processor, and on system level design languages. 2001-2002, he was a research faculty at the University of California at Irvine working on embedded system design. From 2002 till 2015, he has been an assistant, associate, and full professor at Virginia Tech, USA. He co-founded the Center for Embedded Systems for Critical Applications (CESCA) in 2007, and has been a director of the center between 2010 and 2012. In 2015, he joined the Computer Science and Engineering Department of the Indian Institute of Technology Kanpur, India.  He is currently the Poonam and Prabhu Goel Chair Professor, and Dr. Deep Singh and Daljeet Kaur Faculty Fellow at IIT Kanpur.
He received the Ramanujan Fellowship from the Science and Engineering Research Board, Government of India,  the  Presidential Early Career Award for Scientists and Engineers (PECASE) from the White House in 2004, Frederich Wilhelm Bessel Award in 2008 from the Humboldt Foundation, Germany, Virginia Tech Faculty Fellow Award, A distinguished Alumni Award from the State University of New York at Albany, A best paper award at the Asia-Pacific Design Automation Conference, GTE Laboratories Excellence Award,ASEE/ONR Faculty Fellowship in 2005, ASEE/Air Force Senior Faculty Fellowship in 2007, and an Air Force Labs Faculty Fellowship in 2008. Sandeep also has been a visiting faculty at INRIA, France, University of Kaiserslautern in Germany

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