DAC Workshop on System-to-Silicon Performance Modeling and Analysis > Proceedings

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DAC 2015 | San Francisco, CA | June 7, 2015


Keynote : An Accurate Simulation Framework for Thermal Explorations and Optimizations

William Fornaciari (PoliMi, Italy)

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Keynote: Towards Parallel Simulation of Multi-Domain System Models

Rainer Dömer, UC Irvine, USA

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A Cross Layer Approach for Efficient Reliability Management in 3D Stacked Wireless Baseband SoCs

Norbert Wehn (Microelectronic System Design Research Group, University of Kaiserslautern, Germany)

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Using Roofline Models to Analyze the Performance of Realistic Key Value Store Implementations on FPGAs with High Level Synthesis

Kees Vissers and Michaela Blott (Xilinx, USA and Ireland)

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CyberPhysical-System-On-Chip (CPSoC): A Self-Aware SoC Platform for Cross-Layer Reliability

Nikil Dutt (Center for Embedded and CyberPhysical Systems, UC Irvine)

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Connecting temperature to power and performance analysis 

Steve Carlson, Cadence Design Systems, USA

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Enabling Dependable MPSoC Task Migration with On-Chip Interconnect Virtualization

Andreas Herkersdorf (Integrated Systems Lab, Technische Universität München, Germany)

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Dynamic Migration and Performance Optimization of Deterministic Applications Across Platform Components Using Intel® CoFluent™ Studio

Jérôme Lemaitre, Rocco Le Moigne (Intel Corporation SAS, France)

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The FIGAROS Operating System Kernel for Fine-Grained System-Level Energy Analysis 

Timo Hönig, Benedict Herzog, Heiko Janker, Wolfgang Schröder-Preikschat (Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany)

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Extending IP-XACT and UPF to Support ESL to RTL Low Power Design Methodology

Emmanuel Vaumorin, Grégoire Avot (Magillem Design Services; France), Hend Affes, Michel Auguin, Alain Pégatoquet, François Verdier (Univ. Nice Sophia Antipolis, France)

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The Use of High Level IP Power Models Across System Analysis Environments and Teams

Sylvian Kaiser (Docea Power, France)

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Thermal-Aware Power Budgeting for Dark Silicon Chips

Santiago Pagani, Muhammad Shafique (Karlsruhe Institute of Technology, Germany), Jian-Jia Cheny, Jörg Henkel (TU Dortmund, Germany)

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Impact of Time-dependent Variability on the Yield and Performance of 6T SRAM Cells in an Advanced HK/MG Technology

Pieter Weckx, Ben Kaczer, Praveen Raghavan, Francky Catthoor, Guido Groeseneken (IMEC, Belgium)

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Facilitating Cross-Layer Reliability Management through Universal Reliability Information Exchange

Enrico Costenaro1, Domenik Helms2, Nematollah Bidokhti3, Adrian Evans1, Maximilian Glorieux1 and Dan Alexandrescu1 (1IROC Technologies, France; 2OFFIS, Germany; 3OCZ Toshiba, USA)

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Statistical Timing Methodology for Low-Power and Multi-Voltage Designs

Kerim Kalafala, Natesan Venkateswaran, Stephen Shuma, Vladimir Zolotov, Eric A Foreman (IBM Thomas J. Watson Research Center, USA)

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Reliability-Driven Analog Circuit Design using gm/Id Method and Cross Layer Modelling of Aging

Steffen Paul, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen
(Institute of Electrodynamics and Microelectronics, ITEM, University Bremen, Germany)

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