DAC > System and SoC Debug 2010

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System and SoC Debug Integration and Applications
DAC Co-Located Event
June 13, 2010
9:00-17:00
Anaheim, CA


DESCRIPTION


Debug in SoC and electronic systems is a major and ongoing issue for all complex products. Most SoC level ICs and an increasing number of systems include complex instrumentation for debug and related purposes. Different types of debug and instrumentation embedded in a system are varied and often depend both on end application and analysis requirements. Having embedded instrumentation in a design provides a major advantage and compliment to other analysis techniques as it allows real time visibility into the actual system, rather than just models. It is a capability and analysis flow that continues to evolve and improve. Among the capabilities needed in instrumentation and debug flows are tools to support both the automation and integration of instrumentation capability with other analysis methods. Much of the sophisticated infrastructure and analysis tools for design automation may be applied to debug tasks. There are major potential benefits to both the end users and EDA community in reuse of design automation tools, both commercial and open-source, for debug related applications in improving the verification and analysis of SoCs and improving time to market and quality of silicon products.

The types of instrumentation and debug requirements can vary significantly for different types of systems. Software and processor-centric systems have different debug requirements from logic based systems (such as FPGA). High reliability applications such as medical and aerospace have different requirements from entertainment and consumer products, which differ in turn from industrial systems such as networks, and as such require each different investments, both in hardware and development time.

Recent years have seen significant of activity into standardization of the interfaces, features, and methodologies related to SoC and systems debug. These include development work going into the standardization of the debug and software interfaces for multicore and distributed processing systems, which challenge in scaling instrumentation and debug and software development tools to support chips with many cores and the related software and analysis methods required to support them.

This workshop, based on the successful workshops organized by ECSI in 2007, 2008, and 2009, also provides an overview and update into several standards efforts related to SoC and system debug with representation from IEEE working groups including Nexus Forum, IJTAG (IEEE P1687), IEEE 1149.7 as well as working groups within the OCP-IP, Multicore Association, and Eclipse consortiums. It presents the features and commonalities of a vast set of requirements expressed by the system and SoC companies with regard to debug methods and tools will also present and contrast existing commercial debug tools and research into for different applications in these areas.

Chairs

  • Dr Adam Morawiec, ECSI

  • Dr Neal Stollon, HDLDynamics

 


AGENDA


SESSION 1: INTRODUCTION TO CHALLENGES IN SYSTEM AND SOC DEBUG
This session will present major problems in the area of debug of complex systems. An overview of emerging solutions and a “topology map” of the existing standardization activities will be presented, as well as their relations to industry initiatives and de facto standards.
Presenter: Neal Stollon, HDLDynamics

 
SESSION2: INDUSTRY REQUIREMENTS
Industry partners from diverse system companies, SoC providers, and IP providers will express their needs for methods, tools, interfaces, and standards for applications based debug of complex SoC systems. Current practice and available solutions will be discussed, as well as future directions to be undertaken in research, development, and standardization.
Open Roundtable Discussion

SESSION 3: DEBUG DRIVEN STANDARS ACTIVITIES
In this session overview of existing active standardization initiatives and recent progress will be presented together with their achievements, roadmaps, current evolution, and industry support.

IEEE 1149.7 Update

Presenter: Gary Svoboda, Texas Instruments
Abstract: IEEE 1149.7 is a new debug standard which preserves industry investment while providing additional features. It allows debug connection with fewer pins than JTAG, yet can provide additional functionality. Presentation will describe theory of operation, key concepts, and classes of capability. Despite utilizing fewer pins, performance and capability will be preserved. Explanation of how existing silicon and tools infrastructure is preserved. Overview of standards bodies involved in the formation of the new standard. Review of relationship to IEEE P1687, IEEE 1500, and MIPI.

IEEE 5001/Nexus-2010 integration with 1149.7
Presenter: Neal Stollon, HDLDynamics

IEEE P1687 Instrument Connectivity Languages and Interfaces
Presenter: CJ Clark, Intellitech

Application of P1687 is driving Instrument Interface Configurations
Presenter: Scott Hack / Al Crouch, Asset-Intertech

Debug Considerations for OCP 3.0 Standards
Presenter: Neal Stollon, HDLDynamics

SESSION 4: INSTRUMENT APPLICATIONS AND DEBUG TOOLS CAPABILITIES
Industry partners from EDA vendors and debug tools providers will discuss express current and future capabilities and issues of methods, tools, interfaces, and standards for applications debug of complex SoC systems. Current practice and available solutions will be discussed, as well as future directions to be undertaken in research, development, and standardization.

BackSpace: Formal Analysis for Post-Silicon Debug
Presenter: Marcel Gort / Steve Wilston - University British Columbia
Abstract: BackSpace is our new approach for combining formal analysis and some on-chip hardware to help post-silicon debug. Specifically, we are targetting design errors that escape pre-silicon verification and become nightmare post-silicon bugs. BackSpace lets the chip run full-speed in a normal bring-up system, but then provides the effect of having the capability to run backwards from an observed crash (system hang, diagnostic test failure, or other indicator of anomalous behavior), computing an error trace that leads to the problem. In this talk, I'll first review the basics of the BackSpace theory. I'll then present our results in which we have an OpenRISC 1200 implemented on FPGA, with our BackSpace capability added. Finally, I will discuss our recent results to greatly reduce the on-chip overhead of the BackSpace hardware.

On-chip System-Level Visibility for Optimized ARM Platforms & Shorter Time-to-Market
Presenter: Andy Nightingale, Product Manager, Fabric IP Processor Division, ARM
Abstract: With more gates, more software and less time-to-market, it's practically impossible to deliver optimized and differentiated products without the right on-chip visibility implemented in your SoC. ARM will introduce new CoreSight™ technology that delivers cost effective system visibility suitable for inclusion in shipping products to enable an ever larger set of software developers on mobile, multimedia ARM-powered platforms.

Introducing Veridae's Clarus Post-Silicon Validation Suite
Presenter: Brad Quinton, CTO of Veridae Systems, Inc.
Abstract: Increasing integration and complexity of modern IC designs has meant post-silicon validation has become a costly and time consuming effort, even with perfect RTL: the key issue is understanding and finding the root-cause of unexpected behavior. The Clarus Post-Silicon Validation Suite is a powerful toolkit that solves this problem by giving you built-in access to critical state and signal information in your chip. The Clarus Suite is an easy-to-use and easy-to-implement toolkit for on-chip signal capture and post-capture analysis that speeds time to market while reducing development costs.

Dialite Assertion-Based Debug for On-Chip Verification & Analysis
Presenter: Frank Stempski, Temento

Identify Debug Tools
Presenter: Doug Johnson, Synopsys
Abstract: This presentation introduces Identify® Pro software from Synopsys that provides designers with full visibility into complex FPGA and FPGA-based ASIC prototypes enabling them to find bugs at hardware speed and debug the cause of errors in a familiar simulation environment. Identify® Pro is part of the Confirma® ASIC/ASSP verification platform and the presentation will illustrate how to dramatically accelerate the functional debug and verification of FPGAs and ASICs using Identify Pro. Identify® Pro uses patented technology to insert instrumentation to enable debugging within the RTL source code to quickly find bugs that may be sporadic in nature or not exposed because of an incomplete test bench. When a functional bug or assertion failure occurs, the state values of all registers and all memory contents are captured for a user-defined number of clock cycles leading up to the triggering event. The Identify® Pro software works complementary to other verification methodologies, such as assertion-based verification and simulation significantly improving the overall productivity.

SESSION 5: OPEN DISCUSSION - UNIFYING THE DEBUG AND EDA ANALYSIS PROCESS

Session 5A: Panel: Unifying the Debug and EDA analysis process
What are the challenges, what is needed, what are right solutions?

Session 5B: Panel: Application Related Instrumentation
What are different debug challenges for applications and is there a set of common critical IP and tools

The panels will gather opinions from all industry sectors on possible future evolutions required to enable efficient SoC debug able to scale to current and future technology

SESSION 6: DEMOS + NETWORKING
This session will enable parallel demonstrations of EDA and related tools, free discussion, and networking between participants of the workshop.
Demos: Veridae, Mentor Graphics, Lauterbach, Synopsys, Temento
 


REFERENCES


This workshop is based on the established community of people participating to the previous workshops organized by ECSI.

  • System, Software, SoC and Silicon Debug S4D 2009 ConferenceSeptember 24-25, 2009 – Sophia Antipolis, France

  • DAC System and SoC Debug Workshop, June 8, 2008 – Anaheim, Ca.

  • ECSI Institute Workshop on System-on-Chip Debug Standards, April 16, 2007 – Nice, France, http://www.ecsi.org/debug

  • ECSI Institute Workshop on System Debug, March 10, 2008 - Munich, Germany http://www.ecsi.org/sysdebug

 


SPONSORS AND IEEE RELATIONS


The event is co-sponsored by

  • ECSI (Electronic Chips & System design Initiative)

  • IEEE 5001 Nexus

  • OCP-IP Consortium

The event relates to the activities of IEEE

  • IEEE 5001

  • Nexus IEEE IJTAG (P1687)

  • IEEE 1149.7

 


Click here to visit the DAC 2010 official website for more information and for conference registration.

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