High Level Synthesis: Next Step to Efficient ESL Design

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 High Level Synthesis: Next Step to Efficient ESL Design

an ECSI Workshop

January 22, 2009
Yokohama, Japan (in conjunction with ASP-DAC'09 and EDSFair'09)

 

Workshop description (PDF)


Description


The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. Languages like C/C++/SystemC offer high abstraction levels. However, in order to provide the designers with an efficient automated path to implementation, new efficient high-level synthesis tools are required. Several commercial and academic tools are available today: Bluespec from Bluespec, Catapult from Mentor Graphics, Cyber from NEC, Cynthesizer from Forte Design Systems, PowerOpt from ChipVision, PICO from Synfora … GAUT from UBS University, SPARK from UCSD, UGH from TIMA/LIP6, xPilot from UCLA…

The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse.

The workshop will offer an overview of the existing HLS methods and tools, as well as will give insight in the application domains where these tools can be efficiently applied. Successful design cases will be presented to exemplify the practical usage of available HLS technology.

Target Audience:
This workshop on High-Level Synthesis will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline of HLS methods and tools available currently on the market and bring the details on their applicability, performance, and strengths. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users.

Organisers:
Philippe Coussy (Chair)
University of South Brittany UBS, Lab-STICC., Lorient, FR 

Adam Morawiec (Chair)
ECSI, Grenoble, FR
 


Agenda


 
Introduction (8:00-8:15)
Adam Morawiec, ECSI, France 
Philippe Coussy, University of South Brittany, France

Session 1: Architecture and Design Flow I (8:20-9:55)

  • Synthesis and Optimization Foundation for ESL 2.0 (8:20-8:50)

      Jason Cong, UCLA, USA - cong [at] cs [dot] ucla [dot] edu

  • From Executable Specifications to High-Quality Implementations Using Bluespec (8:55-9:25)

      Rishiyur S. Nikhil, Bluespec, USA - nikhil [at] bluespec [dot] com

  • User Guided High level synthesis  (9:30-10:00)

      Frédéric Pétrot, TIMA Laboratory - frederic [dot] petrot [at] imag [dot] fr

Break (10:00-10:10)

Session 2: Architecture and Design Flow II (10:10-11:50)

  • C-based SoC Design Flow with "CyberWorkBench" (10:10-10:40)

      K. Wakabayashi, NEC, Japan - wakaba [at] cad [dot] cl [dot] nec [dot] co [dot] jp

  • How to make algorithmic synthesis as ubiquitous as logic synthesis (10:45-11:15)

      Vinod Kathail, Synfora, USA - vinod [dot] kathail [at] synfora [dot] com

  • Formal Verification in Context of High-Level Synthesis (11:20-11:50)

      Venkatram Krishnaswamy, Calypto, USA - vkrishna [at] calypto [dot] com

Lunch (11:50-12:30)

Session 3: Architecture and Design Flow III (12:30-12:00)

  • Applying SystemC Synthesis to All Your Design Challenges  (12:30-12:00)

      Michael Meredith, Forte Design Systems – USA - mmeredith [at] forteds [dot] com 

  • The CHStone Benchmark Suite for Practical C-Based High-Level Synthesis (13:05-13:25)

      Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Graduate School of Information Science,    
      Nagoya University, Japan

  • Benefits of Model-Based High Level Synthesis with Synplify DSP (13:30-13:55)

      Chris Eddington, Synopsys – Synplicity - chrise [at] synplicity [dot] com

Break (13:55-14:05)

Session 4: Low-Power HLS (14:05-15:35)

  • Power Optimizing High Level Synthesis (14:05-14:35)

      Craig Cochran, ChipVision, Germany - craig [at] chipvision [dot] com

  • New Binding Algorithms for Glitch and Inter-transition Power Reduction (14:40-15:00)

      Deming Chen, Scott Cromar, Gregory Lucas, University of Illinois - dchen [at] illinois [dot] edu

  • High-level Synthesis: Optimizing for Low Power Design (15:00-15:35)

      Andres Takach , Mentor Graphics, USA - andres_takach [at] mentor [dot] com

Panel with participants from User Companies, EDA and Academia (15:35-16:00)

Wrap-up & Close (16:00)

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