System Debug

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 System Debug

an ECSI Workshop

Monday, March 10, 2008 – 9:00-18:00
Munich, Germany
(in conjunction with DATE'08)

office [at] ecsi [dot] org (Get the presentation slides (contact us))
Workshop description (PDF)

Sponsors
OCP International Partnership
ARM
PLS Development Tools
Mentor Graphics
Magillem Design Services
Synplicity
Wind River
Sprint


Agenda



Session 1: Introduction/Challenges (9:00-9:30 [0h30]) 
This session will present an overview and a “topology map” of the existing
standardization activities will be presented, as well as their relations
to industry initiatives and de facto standards

Session 2: Industry Requirements (9:30-10:45 [0h15 each = 1h15])

  • Pre-silicon Debugging Needs for Large Multi-core SoC Designs - SPRINT Project (ST, Infineon, NXP, ARM) – Albrecht Mayer, Infineon
  • ARM - William Orme - CoreSight Product Manager, ARM
  • LSI Logic Requirements – Gary Delp, LSI Logic

Break (10:45-11:15 [0h30])

Session 3: Debug Standards Activities (11:15-13:15 [0h15 each, OCP-IP 0h30])

  • SPIRIT IP-XACT Debug WG – Anthony Berent, ARM
  • Eclipse Device Debugging 1.0: DSF Framework + GDB Debugger - Martin Oberhuber, Wind River
  • OCP Debug Socket for Multi-Core Debugging – Mark Burton, OCP-IP [30min slot]

For the first time ever OCP-IP will announce the release of its Debug Standard. The new standard identifies the signal set for debugging of multiple processor cores connected with the OCP interface. The standard represents a breakthrough allowing designers to distribute debug signals as part of the system interface scheme; rather than wired separately from the data path as had been previously done. This innovative new approach greatly enhances system providers ability to prepare multi-core debug hardware and software that can be easily obtained as IP for new chip designs. Join us as we discuss this exciting new standard. Copies of the standard can be downloaded at www.ocpip.org

  • power.org – Erich Styger, Freescale
  • Target Communication Framework - A Common Tool/Target Communication Infrastructure". – Felix Burton, Wind River
  • SPRINT Multi-Core Debug API - A Standard Debugger Interface for (C-)models and Silicon – Albrecht Mayer, Infineon

Lunch (13:15-14:00 [0h45])

Session 4: Debug Tools Presentations (14:00-16:15 [0h15 each = 2h00])

  • ARM CoreSight
  • Mentor Graphics Debugging Tools – Thomas Ulber, Mentor Graphics
  • The Confirma Platform for ASIC, SoC and IP debug in FPGA – Doug Amos, Synplicity
  • Magillem: IP-XACT Flow Control for Debug – Emmanuel Vaumorin, Magillem Design Services
  • Wind River Debug Solutions - Felix Burton, Wind Driver Systems
  • Lauterbach Debugging Tools – Stephan Lauterbach, Lauterbach
  • Tool Support for Infineons Multi-Core Debug Solution - Thomas Groeger, pls Programmierbare Logik & Systeme
  • Debugging using the SHAPES Virtual Platform – Rainer Leupers, Stefan Kraemer, RWTH-Aachen University

Session 5: Demos + Networking (16:15-18:00 [coffee served during the session])
Parallel demonstrations, free discussion, networking, and next steps in standardization

Venue
NH Hotel München Deutscher KaiserArnulfstrasse 2
80335 MünchenPh: +49.89.99345 681
Fax: +49.89.99345 620

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