System and SoC Debug
an ECSI Workshop
June 8, 2008
(DAC Co-Located Event)
Organizer: Neal Stollon - HDL Dynamics, Dallas, TX
Debug is one of the biggest factors in delaying shipment of a product. The problem is exacerbated with the introduction of multicore technology. SoC-level multicore debug is a topic that has received considerable visibility, due to its importance in improving the verification and analysis of SoCs and improving time to market of silicon products. A fair amount of activity has gone into standardization of the interfaces, features, and methodologies related to multicore debug. There is also considerable discussions and development work going into the standardization of the software interfaces used to debug multicore applications. This represents a challenge in scaling software development tools such as debuggers and simulators to support chips with 10s or 100s of cores. This workshop, based on the two successful workshops organized by ECSI in 2007 and in early 2008, provides an overview into several standards efforts related to multicore debug with representation from IEEE working groups including Nexus Forum, IJTAG (IEEE P1687), as well as working groups within the OCP-IP, Multicore Association, SPIRIT, and Eclipse consortiums. In addition industrial project SPRINT contribution to standardization will be presented. The workshop also shows a vast set of requirements expressed by the system and SoC companies with regard to debug methods and tools. Furthermore, the event will also present and contrast existing commercial debug tools.
9:00-9:30am Session 1: Introduction to Challenges in System and SoC Debug
This session will present major problems in the area of debug of complex systems. An overview of emerging solutions and a “topology map” of the existing standardization activities will be presented, as well as their relations to industry initiatives and de facto standards.
Presenter: Neal Stollon, HDL Dynamics, Dallas, TX
9:30-11:00am Session 2: Industry Requirements
Industry partners from system companies, SoC providers, and IP providers will express their needs for methods, tools, interfaces, and standards for pre-silicon debug of complex multi-core systems. Current practice and available solutions will be discussed, as well as future directions to be undertaken in research, development, and standardization.
- LSI Corp. – Gary Delp, LSI Corp., Rochester, MN
- Debug IP for SoC Debug – Mark Woods, ARM, Sunnyvale, CA
- Freescale – Robert Oshana, Freescale Semiconductor, Inc., Austin, TX
- SPRINT Debug Working Group – Requirements from Infineon, ST, NXP on Debug Methods – Michael Velten, Infineon Tech. AG, Munich, Germany
11:00-11:15am Break and Networking
11:15am-12:45pm Session 3: Debug Standardisation Activities
In this session existing active standardization initiatives will be presented together with their achievements, roadmaps, current evolution, and industry support.
- OCP Debug Socket for Multi-core Debugging - Neal Stollon, HDL Dynamics, Dallas, TX
- IEEE Nexus 5001 - Neal Stollon, HDL Dynamics, Dallas TX
- SPIRIT IP-XACT Debug WG – Gary Delp, SPIRIT Consortium, Rochester, MN
- IEEE 1687 iJTAG - Stylianos Diamantidis, Globetech Solutions and iJTAG 1687 WG
- Linking the Worlds of SystemC and Eclipse, the GreenSocs VPP Project - Mark Burton, Greensocs, Cambridge, United Kingdom
1:30-3:45pm Session 4: Debug Tools & Implementations Presentations
Available tool solutions will be introduced in this session, these short (10-15min) presentations will be followed by demonstrations in the Session 6.
- ARM RealView Debug Tools - Mark Woods, ARM, Sunnyvale, CA
- The Confirma Platform for ASIC, SoC and IP debug in FPGA - Doug Amos, Synplicity, Henley on Thames, United Kingdom
- Magillem: IP-XACT Flow Control for Debug - Emmanuel Vaumorin, Magillem Design Services, Paris, France
- Post-Silicon System Validation and Debug- Paul Bradley, DAFCA, Framingham, MA
- Flexible Debugging of SoC and IP Hardware and System Software on the PROC_SoC Platform - Ralph Zak, Shyam Uma Chander, GiDEL, Inc., Santa Clara, CA
- Debugging using the SHAPES Virtual Platform – Rainer Leupers, Lei Gao, Stefan Kraemer, RWTH-Aachen Univ., Germany
- Nexus-5001 Compatible Real-time Trace for SoC Debug - Akilesh Parameswar, Marc Gauthier, Dhanendra Jani, Tensilica, Inc., Santa Clara, CA
- CJTAG Block/Chip Level Verification Engine – Stylianos Diamantidis, GlobalTech Solutions, Austin, TX
4:00-4:30pm Session 5: Panel: Are we developing right debug solutions to tackle with the real challenges of complex MP SoCs?
The panel will gather opinions from all industry sectors on possible future evolutions required to enable efficient SoC debug able to scale to current and future technology. It will discuss the overlaps in standardization activities that make the entire picture of future industry proven standards very difficult to draw.
4:30-5:15pm Session 6: Demos + Networking
This session will enable parallel demonstrations of EDA tools, free discussion, and networking between participants of the workshop.
Neal Stollon - HDL Dynamics, Dallas, TX
Rainer Leupers - RWTH Aachen Univ., Aachen, Germany
Gary Delp - LSI Corp., Rochester, NY
Mark Woods - ARM Ltd., Sunnyvale, CA
Robert Oshana - Freescale Semiconductor, Inc., Austin, TX
Michael Velten - Infineon Technologies AG, Munich, Germany
Mark Burton - GreenSOCs, Cambridge, United Kingdom
Doug Amos - Synplicity, Inc., Oxfordshire, United Kingdom
Emmanuel Vaumorin - Magillem Design Services, Paris, France
Paul Bradley - DAFCA, Inc., Framingham, MA
Lei Gao - RWTH Aachen Univ., Aachen, Germany
Stefan Kraemer - RWTH Aachen Univ., Aachen, Germany
Akilesh Parameswar - Tensilica, Inc., Santa Clara, CA
Marc Gauthier - Tensilica, Inc., Santa Clara, CA
Dhanendra Jani - Tensilica, Inc., Santa Clara , CA
Stylianos Diamantidis - GlobalTech Solutions, Austin, TX
Ralph Zak - GiDEL, Inc., Santa Clara, CA
Shyam Uma Chander - GiDEL, Inc., Santa Clara, CA