The New Wave of the High Level Synthesis

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  The New Wave of the High Level Synthesis

an ECSI Workshop

Friday, March 14, 2008 – 8:30 -16:45
Munich, Germany
(in conjunction with DATE'08)

Workshop description (PDF)
Agenda (PDF)
Abstracts (PDF)

Sponsors
ECSI
L.E.S.T.E.R. (Laboratoire d'Electronique des Systèmes Temps Réel)

Description:
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimised gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioural one. Languages like C/C++/SystemC offer high abstraction levels. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic tools are available today: Bluespec from Bluespec, Catapult from Mentor Graphics, Cyber from NEC, Cynthesizer from Forte Design Systems, PICO from Synfora … GAUT from UBS University, SPARK from UCSD, UGH from TIMA/LIP6, xPilot from UCLA…

The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse.

Target Audience:
This workshop on High-Level Synthesis will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline of HLS methods and tools available currently on the market and bring the details on their applicability, performance, and strengths. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users.

Agenda:
0830 – 0840 Introduction
P Coussy, University of South Brittany, FR and A Morawiec, ECSI, FR

SESSION 1: EDA TOOL PRESENTATIONS

0845 - 0900 Catapult Synthesis: a Proven Approach for the Creation of
Complex Hardware Designs
Bollaert, Mentor Graphics FR

0905 – 0920 How to Make Algorithmic Synthesis as Ubiquitous as Logic
Synthesis
V Kathail, Synfora, US

0925 – 0940 Cynthesizer: the Forte SystemC synthesis tool
 M Meredith, Forte Design Systems, US

0945 – 1000 New Opportunities for High-Level Synthesis
J Cong, UCLA/AutoESL, US

1000 – 1015 BREAK

SESSION 2: RESEARCH DIRECTIONS

1020 – 1040 HLS and Cost of Design
R Gupta, UCSD , US

1045 – 1105 Multi-Mode Architecture Design with High-Level Synthesis
 P Coussy, University of South Brittany, FR

1110 – 1130 Ant Colony Optimization for High Level Synthesis
R Kastner, UCSB, US

1135 – 1155 User Guided High level synthesis
F Pétrot, TIMA Laboratory, FR

1200 – 1300 LUNCH

1300 – 1430 SESSION 3: POSTERS / DEMONSTRATIONS / INTERACTIVE PRESENTATIONS

1430 – 1445 BREAK

1445 – 1645 SESSION 4 : THE FUTURE OF HIGH-LEVEL SYNTHESIS

The Limits of Current HLS Offer : What is Needed for a Wider Adoption
P Urard, STMicroelectronics, FR

"All-in-C" SoC Synthesis and Verification with CyberWorkBench
K Wakabayashi, NEC, JP

Enabling DSP System Designs with High Level Design Methodologies
& Tools
J Heighton, Xilinx, IR

Industrial Usage of High-Level Synthesis
W Ecker, Infineon , DE

Synthesis Semantics for SystemC
 A Takach, Chair of the OSCI Synthesis Working Group, US

PANEL DISCUSSION
With all session 4 presenters

1645 CLOSE

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