Reconfigurable Systems-on-Chip

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  Reconfigurable Systems-on-Chip

an ECSI Workshop

January 18, 2007
Hotel Ibis/Gare CDG Airport - Paris, France

See the official call


Description


 

This event organized by ECSI, TU München and OFFIS is one of the series of workshops that address advanced topics in system design. 

This time the focus is on reconfigurable Systems-on-Chip. Those systems are typically embedded devices implemented on FPGA-based platforms which support reconfiguration in the field or even during run-time.

The workshop will cover in a dedicated Session industry needs and requirements to understand current and future application scenarios for reconfigurable systems in their various flavors and domains.

The main session is dedicated to research activities presented by academic as well as industrial contributors.

Future ASIC-based SoCs will have to cope with increasing challenges. The challenges are rooted in application-driven requirement (e.g. changing standards) or manufacturing problems like transient errors and technology parameter variations. This might lead even for traditionally ASIC-based SoCs to adopt FPGA-based elements and thus to make use of reconfiguration techniques in order to adapt the architecture. So reconfiguration may grow into the ASIC business.

  • Rapidly changing application standards in fields like communications and information security ask for frequent modifications of systems in the field. Software updates may often not be sufficient to keep devices in the market, but hardware redesigns are quite expensive, due to increasing mask costs for ASICs. FPGA-based reconfiguration seems here to be a cost effective solution to keep devices up-to-date. 

  • Adaptive devices: In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches require more than just software based changes but also adaptation of the application specific hardware components. Today’s FPGA generations already offer partial reconfiguration at runtime but current design practices hardly exploit these capabilities. With new methodologies these capabilities may enable groundbreaking innovations in embedded system design.

  • With technologies at 45nm and below, manufacturing problems like dopant distributions, oxide thickness variations, will strongly influence electrical parameters of transistors (delay times will vary, timing limits, crosstalk sensitivity), leading to dramatically reduced yield rates. Here Self-healing SoCs with autonomic self-control based on reconfigurable technologies promises a way out.

  • Transient errors caused by Alpha particle radiation is beginning to bother FPGA and ASIC designs, as well. Future technologies will suffer increasingly from radiation induced transient errors in logic circuits and registers. Error detection and correction mechanism can benefit from reconfiguration capabilities.

The efficient integration of reconfiguration in SoCs requires powerful design tools. Hence in the last session an overview to existing and future EDA support for reconfigurable Systems-on-Chip will be discussed.

Although several approaches will be illustrated during the talks, these can be just very first steps.
Many questions are still open. The focus of the workshop is to interactively identify

  • the design space for reconfigurable SoCs,

  • the currently available design tools and methods,

  • the current state of dynamic hardware reconfiguration,

  • the key problems to be solved.

So we would like to invite you to participate and contribute to a fruitful discussion during this workshop on reconfigurable SoCs


Agenda



Session 1: Introduction
Overview of problems, expectations, tendencies, emerging solutions.
Speaker:
Walter Stechele, TUM

Session 2: Industry Needs and Requirements
System companies overview of needs, types of applications, products.
What technical and business trade-offs need to be considered?
Reconfigurable SoC from a user perspective.
Invited speakers:

  • "Reconfigurable Computing Needs From an Industrial Perspective" – Nikos Voros, Intracom
  • Philippe Butel, MBDA• Nizar Romdhane, ARM
  • "Applications for Reconfigurable Systems-on-Chip in Telecommunication Networks" - AxelSchneider, Lucent Technologies
  •  “Perspectives of Reconfigurable Technology Application in Software Defined Radio, Security andImage Processing Areas” - Daniel Maufroid, Thales

Session 3: Research Activities
Current research issues in the area of dynamically reconfigurable SoCs.
Invited speakers:

  • "Application programming design flow for the MORPHEUS dynamically reconfigurable platform" - Philippe Bonnot, Thales• "Modelling and Synthesis of adaptive SoC" - Frank Oppenheimer, OFFIS
  • "AutoVision - A Run-time Reconfigurable MPSoC Architecture for Future Driver AssistanceSystems" - Walter Stechele, TU Muenchen
  • Juergen Becker / Michael Huebner, U Karlsruhe• "Research on Dynamic Reconfigurable Computing in Germany" - Juergen Teich, U Erlangen
  • "Lossy Synthesis for Reconfigurable Systems" - Peter Cheung, Imperial College• Kari Tiensyrjä / Yang Qu, VTT Electronics
  • Mladen Berekovic, IMEC• Gordon Brebner, Xilinx
  • Amanda Tannahill, ISLI (TBC)• Rainer Hartenstein, U Kaiserslautern (TBC)

Session 4: EDA Support
Outlook on reconfigurable SoC by EDA companies.
Invited speakers:

  • Jean-Marie Saint-Paul, Mentor Graphics
  • Florian Schaefer, Cadence
  • Bart Vanthournout, CoWare (TBC)
  • Chris Sullivan, Celoxica (TBC)
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