Users Experience with TLM: TLM Untimed Modelling and Performance Estimation with SystemC

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Users Experience with TLM:
TLM Untimed Modelling and Performance Estimation with SystemC

an ECSI Workshop

June 8, 2006
Paris, France

Workshop description (PDF)


DESCRIPTION


The objective of the workshop is to hear from users of SystemC and TLM infrastructure "first hand". To share best practise and to feedback to both internal infrastructure providers and tool vendors what could be better. The workshop will focus on two levels of modelling abstraction: TLM un-timed modelling (typically expected to be used for software development, sometimes termed Programmers View (PV) modelling) and TLM timed modelling (typically expected to be used for performance estimation, sometimes termed PV-T modelling). The workshop will be particularly interested in uses of these and other types of models outside of the "expected" use cases!

The workshop will give the opportunity to the users to present how they use SystemC and the TLM standard, and what they would recommend as best practice. The format of the presentations should include :
  • What was the application areaWhat tools and infrastructures were used
  • What problems were encounteredWhat lessons learned
  • What needs to be modified in the standardWhat additional tools or infrastructure would help
  • How together a complete and consistent modelling, verification, and implementation (both SW and HW) flow could be constructed.

The workshop will also enable those involved in building tool chains and infrastructure to present their current R&D activity.

The EDA companies will present their tools in parallel demo sessions.

There will also be time allocated to "networking sessions" and panels, in order to enable extensive discussion.
 


AGENDA



Part 1: TLM-Untimed

TLM-Untimed deployment for functional HW engineers and SW developers: OSCI TLM 1.0 and other standards that are going to be compatible with it (SPIRIT, OCP), use models, open source classes built on OSCI TLM standard e.g. TLM_TAC.

Session 1: Brief Introduction to TLM (Alain Clouard, STMicroelectronics) (30min)

Session 2: TLM-related Standardisation Summary (45min)
OSCI SystemC TLM Evolution ( Alain Clouard, ST)SPIRIT for TLM (Nizar Romdhane, ARM)
OCP-IP Modelling in TLM (Mark Burton , GreenSoCs, OCP)

Panel discussion (20min)

Session 3: Users Experience with SystemC TLM (100min)

Invited partners from PRODUCT DIVISIONS:

  • STMicroelectronics Modelling Experience
  • FireWire and USB IP Blocks Modelled with SystemC TLM - Adam Bitniok, Ireneusz Sobanski, Evatronix
  • TLM Modelling Experiences for Early Analysis in the ICODES Project - Francesca Tonetta, Siemens
  • New Silicomp Activities and Services in SystemC/TLM - Vania Joloboff, Silicomp
  • Infineon Modelling Experience (TBC)Panel discussion (30min)

Part 2: Performance Estimation with SystemC - TLM-Timed

Performance estimation with SystemC, centered (but not exclusive) on TLM-Timed / PV-T (with possible complements on BCA/CABA interconnect or few IPs, in a TLM-Timed SoC). Again, focus on standards, and use models.

Session 4: Performance Estimation with SystemC (80min)

  • Performance Estimation with SystemC TLM - STMicroelectronics
  • ESL Interfaces to the ARM Models and System-level Technology - Nizar Romdhane, ARM
  • Timing, Analysis, and the OSCI TLM - Adam Rose, Mentor Graphics
  • Infineon performance modelling experience presentation (TBC)

Panel discussion (30min)

Part 3: TLM Research Activities

Session 5: TLM-related Research Activities (80min):

  • Separating Functional and Timed Aspects in Transactional Abstraction Levels - Jerome Cornet, Verimag
  • OSSS-Channels: Synthesisable TLM Concepts - Cornelia Grabbe, OFFIS
  • Aimen Bouchhima, TIMALETI (TBC) 

Part 4: Parallel Tool Demos + Networking Discussion

Session 6: EDA Demonstrations Introduction (5min per EDA company)

Session 7: Parallel Demonstrationa + Networking Discussion (90min)

Invited partners: Cadence, Mentor, Summit, Celoxica, SpiraTech, VaST

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