High-Level Synthesis

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 High-Level Synthesis

an ECSI & UBS Workshop

September 18, 2006 – 9:00 -18:30
TU Darmstadt, Germany

(in conjunction with FDL)

 

See the official call

The successful usage of Hardware Description Languages like VHDL and Verilog in the design flow is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction despite the failure of previous attempts to behavioural synthesis from higher-level descriptions.

Languages like C or SystemC offer high abstraction level. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic C/C++/SystemC–based tools are available today: the Agility Compiler and DK Design Suite from Celoxica, eXCite from Y Explorations, CatapulC from Mentor Graphics, Cyber from Nec, PICO from Synfora, Cynthesizer from Forte Design Systems, Cascade from Critical Blue… SPARK from the UCSD, GAUT from the UBS…

The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows to better managing the system design complexity, to verify earlier in the design process and to increase code reuse.

Thus, users formulate several crucial questions with regard to system synthesis:
  • Is the so-called “high-level synthesis” an appropriate and efficient solution to get to the implementation?
  • Is it optimal (how efficient is the RTL architecture, targeted to downstream synthesis tools)?
  • What benefit can users gain and at what price: how does it influence the designer productivity, the design
  • flow and the way of exploring multiple implementation alternatives, trade-off management…?
  • What about the verification flow (reuse of test-bench, back-annotation from implementation to
  • specification)?
  • How can IP reuse be strengthened by high-level synthesis: automatic retargeting to different technologies, exploration of implementation alternatives and trade-offs?

The ECSI & UBS Workshop on High-Level Synthesis HLS will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline (as complete as possible) of HLS methods and tools available currently on the market bring the details on their applicability, performance and strengths. Finally, the event will create a discussion platform for experience exchange between participants.

The following Companies/Universities will be involved:
Daniel Gajski, University of California, Irvine, UCI
Stephen A. Edwards, Columbia University
R. Gupta, University of California, San Diego, UCSD
Pascal Urard, STMicroeletronics
Thales Communications
France Telecom
Philips Semiconductors
Panasonics Communication
Jean-Marie Saint-Paul, Mentor Graphics
Chris Sullivan, Celoxica
Kazutoshi Wakabayashi, NEC
Mike Meredith, Forte Design
Richard Taylor, Critical Blue
Pat Sheridan, Jerome Bring, CoWare
Grant Martin, Tensilica
Vinod Kathail, Synfora
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