Verification Futures 2012 Presentation Slides

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Verification Futures 2012
European Verification Week

November 19, 21, 22
UK - France - Germany

co-organized by TVS and ECSI


 

Windsor, UK

Mentor Graphics - Harry Foster, Chief Scientist
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 

Synopsys - Janick Bergeron, Scientist and Fellow
Title: Will Everything Start to Look like a SoC?

 

Panel Session:  Users - Our Top Verification Challenges

 

User Presentations

Title:  Transaction Level Assertions in UVM

Title:  Datapath Property Checking at Imagination

 

EVE - Lauro Rizzatti, Emulation & Verification Engineering S.A
Title:  Emulation Prime Time in SoC Design Verification

 

Jasper Design Automation - Stefan Staber, Staff Field Application Engineer
Title: Leveraging Formal Verification Throughout the Entire Design Cycle

 

Doulos - John Aynsley, CTO
Title: UVM Now or Never?

 

Cadence - Nick Heaton, Senior System and SoC Solutions Architect
Title: The Driving Forces & Industry Innovaton in SoC Analysis and Verification

 

SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
Title:  Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 

Aldec Inc - Jacek Majkowski, Senior Hardware Engineer
Title:  SCE-MI obviously. But which one?

 

Grenoble, France

Mentor Graphics - Harry Foster, Chief Scientist
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 

Panel Session: Challenge papers - Our Top Verification Challenges

 

Synopsys – Janick Bergeron, Scientist and Fellow
Title:  Will everything start to look like a SoC?

 

User Presentations

 

EVE - Luc Burgun, CEO and President, Emulation & Verification Engineering S.A
Title:  Emulation Prime Time in SoC Design Verification

 

Jasper Design Automation - Barbara Jobstmann, Senior Field Applications Engineer
Title: Leveraging Formal Verification Throughout the Entire Design Cycle

 

Breker Verification Systems Inc - Frederic Krampac, Senior Applications Engineer
Title: Break Your SoC with Automatically Generated C Test Cases

 

SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
Title:  Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 

Cadence - Nick Heaton Senior System and SoC Solutions Architect
Title: The Driving Forces & Industry Innovaton in SoC Analysis and Verification

 

Munich, Germany

Mentor Graphics - Harry Foster, Chief Scientist
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 

Panel Session: Challenge Papers - Our Top Verification Challenges

  • Infineon – Wolfgang Ecker, Principle Engineer (slides unavailable)

 

Synopsys – Janick Bergeron, Scientist and Fellow
Title:  Will everything start to look like a SoC?

 

User Presentations

 
 

 

EVE - Luc Burgun, CEO and President, Emulation and Verification Engineering S.A, EVE.
Title:  Emulation Prime Time in SoC Design Verification

 

Jasper Design Automation - Carlo Del Giglio, Staff Field Applications Engineer
Title: Leveraging Formal Verification Throughout the Entire Design Cycle

 

Doulos – John Aynsley, CTO
Title: UVM Now or Never?

 

Breker Verification Systems Inc. – Jörg Große, Applications Engineer
Title: Close Your Coverage Loop with Graph-Based Scenario Models

 

SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
Title: Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 

Cadence - Nick Heaton, Senior System and SoC Solutions Architect
Title: The Driving Forces & Industry Innovaton in SoC Aanalysis and Verification


Sponsors

 

 
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