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Verification Futures 2012
European Verification Week

November 19, 21, 22
UK - France - Germany

co-organized by TVS and ECSI

United Kingdom (Windsor)
France (Grenoble)
Germany (Munich)



Windsor, UK - Program

 

Time Agenda
08:30 Arrival: Refreshments and Networking
09:15 Introduction:  Mike Bartley, TVS
09:20 Mentor Graphics - Harry Foster, Chief Scientist
 
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 
Abstract:   A remarkable emergence of new advanced verification techniques, methodologies, languages and new standards has occurred in the past ten years. And recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions.  Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.
 
Yet for many projects, the process of evolving a team's functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.
 
This presentation discusses techniques for evolving your SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.
 
Biography: Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored six books on verification--including the 2008 Springer book Creating Assertion-Based IP.  Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
 
10:00 Panel Session:  Users - Our Top Verification Challenges
 

Biography: Tim is shortly due to return from a year in Bangalore where he is working on methodology improvements for verification and validation of IP for Infineon’s Aurix family of microcontrollers.  Prior to this he was CPU verification lead for Infineon’s TriCore performance cores. He has around 12 years experience in verification, including several years as a formal verification expert within Infineon.  He has published on verification and formal methods in several conferences, including DAC, DesignCon, DVCon and iFM, and has served on the Technical Panel Committee for DesignCon.  He has also published in leading journals on Information Theory and Mathematics and has a Ph.D. in Pure Mathematics.

Biography: After graduating in 2000 with a masters in Theoretical Physics from the University of Exeter  Andy began his career as a verification engineer for ST Micro.  As part of the SuperH team he focused on the verification of multiple SH4 and SH5 cores within ST and the subsequent SuperH Inc until joining the original silicon team of Icera Inc in 2004.  After developing several generations of soft modem products Icera was acquired by nVidia in 2011 and integrated into the mobile division. Within nVidia he currently leads the function verification efforts for the modem team.
 
Biography: Geoff graduated from Oxford University with a DPhil in formal verification in 1988. He worked for STMicro for 10 years where he spent much time implementing model checkers and formal equivalence checkers. He joined Element14 in 1999 where he founded the verification team and was Verisity’s first European customer. Since E14 was acquired by Broadcom, Geoff has developed a unified chip verification environment which is used across the Broadband Communications Group. He now runs Broadcom’s FirePath DSP processor development programme and chairs NMI’s Microelectronics Design Advisory Board.
 
Biography: Digital design complexity of Wolfson’s Audio Hubs has risen rapidly over the last few years. They are multi-million gate designs today and are likely to grow further in the future. This increased complexity meant that the approach for design and verification methodologies used during the development process of Wolfson’s recent products had to evolve.
Andre is responsible for methodology improvements for digital design as well as verification in Wolfson. With 7 years of verification experience and his passion for methodology he regularly presents at conferences. Prior to Wolfson, Andre worked for a full custom design house (MAZ Brandenburg GmbH) as a digital design/verification lead and has a degree (Dipl.-Ing.) in computer engineering of the Technical University of Berlin.
 
Biography:  Steve Holloway is currently Senior Verification Engineer within the Methodologies group of Dialog Semiconductor.  He has led the verification of various large-scale consumer SoC projects and is experienced with various Hardware Verification Methodologies including eRM, OVM and UVM.  Steve has previously worked for Doulos, NXP and Trident Microsystems.

 

10:40

Synopsys - Janick Bergeron, Scientist and Fellow

Title: Will everything start to look like a SoC?
 
Abstract:
Recent Mobile and Processor designs show remarkable similarity to each other. Consider the example of the ARM big.LITTLE configuration of A15 and A7 cores, which provide the ability to switch between high-performance and low power, or the Intel Core i7 with its mobile and desktop configurations.

With the convergence of these two previously distinct design types, the emerging result looks a lot like an SoC every time and, understandably, the largest and most complex SoCs tend to grab the headlines, but they also drive the verification agenda.

The efficiencies and capabilities of verification tools which most benefit SoC designs, are also mighty useful for other types of design, including those more typically found in European design centers, including automotive or industrial designs.

To face these challenges in the future, how will the demands of expanding scale and complexity in the midst of shrinking geometries and timescales drive advanced verification technologies into the mainstream? How quickly will ever greater use of complex Interface and bus protocols drive the adoption of Verification IP standardised around SystemVerilog? Can we continue to scale gate-level simulation or will we look to more predictive RTL simulators to find bugs earlier in the design flow? Can high-level static techniques reduce the demands on RTL simulation itself?

In fact, when we verify in the future, will everything look like a SoC?

In this presentation, Janick Bergeron, Fellow at Synopsys, spreads the verification Tarot to discern the emerging verification technologies, and how unparalleled R&D investment at Synopsys and partnership with leading practitioners is driving several unique technology breakthroughs which will overcome the verification challenges of the near future.

Biography:
Janick Bergeron is a Scientist at Synopsys. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models. He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Nortel Networks. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.

11:00 Refreshments and Networking
11:30

User Presentations

Title:  Transaction Level Assertions in UVM

Abstract:  The UVM Methodology embodies a central concept of transaction-level modelling (TLM) to abstract the way communication in a design is modelled. A transaction can be used to represent a complex series of signal transitions such as a bus operation or transfer of data over an external interface. System Verilog Assertions (SVA) provide a concise and powerful notation to specify sequential behaviour and to evaluate that behaviour at discrete points in time. Performing SVA based checks on the temporal relationship between transactions offers the potential to succinctly verify the design at a higher level of abstraction. The presentation describes a novel approach for creating assertions at the transaction level by making a bridge between dynamic (class-based) and static (module-based) verification code. Some example TLM assertions are shown which can verify complex sequential behaviour, express performance constraints, or check system-level interaction in a concise manner.Biography:  Steve Holloway is currently Senior Verification Engineer within the Methodologies group of Dialog Semiconductor.  He has led the verification of various large-scale consumer SoC projects and is experienced with various Hardware Verification Methodologies including eRM, OVM and UVM.  Steve has previously worked for Doulos, NXP and Trident Microsystems.

Title:  Datapath Property Checking at Imagination

Biography:  Theo Drane started working for the datapath consultancy Arithmatica in 2002 after completely a Mathematics degree from the University of Cambridge, UK. He moved to Imagination Technologies in 2005 where his interests are datapath optimisation, verification and validation.   After a two year sabbatical to work for an independent financial provider, Markit, he returned to Imagination to head up their datapath team while studying for a PhD at Imperial College London.

 

12:30 EVE - Lauro Rizzatti, Emulation & Verification Engineering S.A
 
Title:  Emulation Prime Time in SoC Design Verification

 
Abstract:  Hardware emulation has been known for well over 20 years.  Originally and during the 90’s it was limited to performing functional verification of the largest designs of the time, namely, CPU and graphics designs.  But starting in early 2000, and gradually until the end of the decade, it moved outside the original niche and developed into a major verification tool for most electronic designs in all markets.

We anticipate that in the next decade it will become the mandatory verification/validation technology for any new embedded design.  This presentation discusses the evolution of hardware emulation, and it highlights features and benefits in its deployment for hardware verification and embedded software validation of System-on-Chips (SOC) designs.

The presentation will conclude with the description of few customer successes in the adoption of hardware emulation.
 
Biography:  Dr. Lauro Rizzatti has more than 30 years of experience in the EDA and ATE industries, where he held responsibilities in management, product marketing, technical marketing, and engineering. Prior to joining EVE he held various positions in companies such as Get2Chip, Synopsys, Mentor Graphics, Teradyne, Alcatel, and Italtel. Lauro has published several articles and technical papers in the trade press and has presented at numerous international technical conferences. Lauro holds a doctorate in Electronic Engineering from the Universita` degli Studi di Trieste, Italy.
 

13:00 Lunch and Networking
14:00
 
Title: Leveraging Formal Verification Throughout the Entire Design Cycle
 
Abstract:  Formal is typically seen as a point tool with limited scope and is usually only applied to a small subset of design and verification challenges. However, with the right supporting technologies and features, the benefits of formal verification can be leveraged throughout all stages including:
 
  • Stand-alone verification of architectural protocols
  • Designer sandbox testing for RTL development
  • End-to-end data packet integrity
  • SoC connectivity and integration verification
  • Root-cause isolation and full proofs during post-silicon debug
 
Traditional verification methods of the above areas are becoming more of a challenge as design complexity increases, but formal verification can be a valuable addition. For example, applying formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about Jasper’s unique formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. We’ll explore new areas that Jasper Formal technologies are addressing including coverage closure, system-level deadlock, low power, and sequential equivalency checking.  When applied intelligently, Jasper formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.
 
Biography:  Stefan Staber is a Staff Field Applications Engineer for Jasper Design Automation. Prior to joining Jasper, he worked as an Applications Engineer for an EDA company in Munich, Germany. Stefan holds a PhD in Computer Science from Graz University of Technology, Austria.
 
14:20

Doulos - John Aynsley, CTO

Title: UVM Now or Never?

Abstract: This presentation highlights the reasons why you should (or in a few cases should not) be adopting UVM right now, and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL.

Biography: John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specialising in VHDL, SystemVerilog, and SystemC. He is co-author of the IEEE 1666-2011 SystemC standard.

14:40

Cadence - Nick Heaton, Senior System and SoC Solutions Architect

Title: The Driving Forces & Industry Innovaton in SoC Analysis and Verification

Abstract:The massive integration of capabilities in mobile devices has produced an explosion in the complexity of the SoCs that drive them. These devices regularly exceed 100 substantial IP blocks and 100+ millions of gates of logic. Multi-core processing is necessary to drive the growth in real-time consumer applications. The number of variables for architecting the SoCs is beyond what can be evaluated statically or with spreadsheets. The industry is exploring how to leap ahead in productivity and to manage the complexity of the system architecture, system development, and system verification.

This talk will cover the leading edge innovations and major industry trends in these areas. From earlier dynamic architectural analysis, software driven verification, through the increasing use of advanced verification automation. The world of verification is rich with innovation!

Biography: Nick Heaton is an ASIC and EDA veteran with more than 25 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honors in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as ARM® and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering. Nick currently works in the Cadence Research & Development organization as a Senior Solutions Architect with special responsibility for Interconnect Verification Automation and Performance Analysis.

15:00 SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
 
Title:  Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 
Abstract:  Functional qualification – the process of finding weaknesses in and measuring the effectiveness of a verification environment through a fault injection process – has become an accepted and sometimes required aspect of verification since it was pioneered by the Certitude™ product from SpringSoft in 2005.  This unique approach is in daily use by companies worldwide to assess and improve their simulation environments.  The same approach can be applied to formal verification environments.  Given a set of properties, if the RTL functionality is changed through the injection of a fault yet all of the properties still “pass” when proven by a formal verification tool, what does it indicate – a missing property, an incorrectly-described property, an over-constrained environment?  This presentation will explore how functional qualification can be extended to assess and improve formal verification environments to provide a unique perspective on their completeness and correctness.
 
Biography:  Jean-Marc Forey has a degree from the ‘Ecole Nationale Supérieure de Physique de Strasbourg’ (1988). He has held hardware development positions in Thomson CSF, Matra Marconi Space, Philips TRT,
Hewlett-Packard. He has been Senior Verification Application Engineer for Synopsys, then application engineer director in Certess from 2005 until their acquisition by SpringSoft in 2009. Since then he has been Technical Marketing Manager in SpringSoft for Certitude.
 
15:40 Refreshments and Networking
16:10 Aldec Inc - Jacek Majkowski, Senior Hardware Engineer
 
Title:  SCE-MI obviously. But which one?

 
Abstract:  SCE-MI stands for Standard Co-Emulation Modeling Interface and is the Accellera standard for bridging two realms: untimed (HVL, on host) and timed (HDL, in emulator).  It eliminates any communication bottleneck using synthesizable transactors. Since SCE-MI 2, three use models are available: macro-, function and pipes-based. Differences, use cases and recommendations are described.
 
Biography:  Jacek Majkowski is a senior hardware engineer from Aldec, where he is a specialist in SCE-MI co-emulation. Prior to this position, he spent 7 years in the field of hardware assisted verification. Jacek received his Master of Science in Electrical Engineering from AGH University of Science and Technology in Krakow, Poland.
 
16:40 Panel Session:  The EDA response
17:25

Concluding Remarks from Platinum Sponsors

(Mentor Graphics, SpringSoft Inc, Cadence, EVE and Aldec)

 

17:40 Meet the Sponsors in the Exhibition Area
18:15 End of Conference

Participating companies in Windsor include:


Grenoble, France - Agenda

 

Time Agenda
08:30 Arrival: Refreshments and Networking
09:15 Introduction:  Mike Bartley, TVS
09:20 Mentor Graphics - Harry Foster, Chief Scientist
 
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 
Abstract:   A remarkable emergence of new advanced verification techniques, methodologies, languages and new standards has occurred in the past ten years. And recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions.  Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.
 
Yet for many projects, the process of evolving a team's functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.
 
This presentation discusses techniques for evolving your SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.
 
Biography:   Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored six books on verification--including the 2008 Springer book Creating Assertion-Based IP.  Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
 
10:00 Panel Session: Challenge papers - Our Top Verification Challenges
Biography: Laurent received his PhD on formal verification of microprocessors in 1996 from the University of Nice – Sophia Antipolis, France. Laurent then worked on modeling techniques and semi-formal verification for Texas Instruments, then on high-level synthesis for Esterel Technologies. He has been working for ARM for 6 years, first as a modeling engineer, now as formal verification expert. As such, he is building the strategy for a wider usage of formal verification within ARM.
 
Biography: Thomas joined micro-electronic as a formal verification engineers in the late 90’s. In 2005, he joined the wireless design community as a verification manager. He’s been exposed to the very fast evolution of the verification world, from standard testbenches to constrain-random approach, and tackling low-power verification challenges. He’s now design manager in ST-Ericsson, responsible for the digital SOC designs of the company.
 
Biography: Thomas joined micro-electronic as a formal verification engineers in the late 90’s. In 2005, he joined the wireless design community as a verification manager. He’s been exposed to the very fast evolution of the verification world, from standard testbenches to constrain-random approach, and tackling low-power verification challenges. He’s now design manager in ST-Ericsson, responsible for the digital SOC designs of the company.
 
Biography: Christophe is the Functional Verification Group Manager in the Digital Section and it’s his mission to provide ST & STE divisions with Functional Verification Best-Class means to enhance development time and quality products using our “critical mass” of expertise and partnerships. He achieved the INSA Engineer’s degree (Electricity) at Institut National des Sciences Appliquées de Lyon (INSA) in 1992 and went on to work at Thomson CMS and Alcatel CIT before joining STMicroelectronics in 1995.

 

10:40 Synopsys – Janick Bergeron, Scientist and Fellow
 
Title:  Will everything start to look like a SoC?

 
Abstract:  Recent Mobile and Processor designs show remarkable similarity to each other. Consider the example of the ARM big.LITTLE configuration of A15 and A7 cores, which provide the ability to switch between high-performance and low power, or the Intel Core i7 with its mobile and desktop configurations.
 
With the convergence of these two previously distinct design types, the emerging result looks a lot like an SoC every time and, understandably, the largest and most complex SoCs tend to grab the headlines, but they also drive the verification agenda.
 
The efficiencies and capabilities of verification tools which most benefit SoC designs, are also mighty useful for other types of design, including those more typically found in European design centers, including automotive or industrial designs.
 
To face these challenges in the future, how will the demands of expanding scale and complexity in the midst of shrinking geometries and timescales drive advanced verification technologies into the mainstream? How quickly will ever greater use of complex Interface and bus protocols drive the adoption of Verification IP standardised around SystemVerilog? Can we continue to scale gate-level simulation or will we look to more predictive RTL simulators to find bugs earlier in the design flow? Can high-level static techniques reduce the demands on RTL simulation itself?
 
In fact, when we verify in the future, will everything look like a SoC?
 
In this presentation, Janick Bergeron, Fellow at Synopsys, spreads the verification Tarot to discern the emerging verification technologies, and how unparalleled R&D investment at Synopsys and partnership with leading practitioners is driving several unique technology breakthroughs which will overcome the verification challenges of the near future.
 
Biography:  Janick Bergeron is a Scientist at Synopsys. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models. He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Nortel Networks. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.
 
11:00 Refreshments and Networking
11:30 User Presentations

Abstract: Today’s Mixed Signals SoCs contain several digitally controlled analog blocks. The number of interface signals between the analog and digital parts are continuously increasing. For building a state-of-the-art UVM-based verification environment it is required that the UVC representing the analog behavior is available at a very early stage in the design phase. Ideally, the UVC can be used by the designers from the beginning on.

In order to provide a UVC at an early design stage we propose to extend the standard UVCs with the following features. For the designer it is very helpful if he is able to stimulate the analog/digital interfaces either directly or to drive them from an analog model. Directly driving the analog/digital interface is of particular interest as the analog model is in general not available at the point in time when design starts. Providing the directly driven stimulus, still allows to use the UVM environment including the analog UVC for basic verification immediately. Once the analog model becomes available the UVC can switch from directly driven to stimuli provided by the analog model.

Additionally, it must be possible that the UVC can cope with the unavoidable interface changes during the design phase in an appropriate and error-free way. This can be best achieved by using automated code generation in order to combine handwritten and auto generated code as it has been shown in [DVCON2012].

In this presentation we present the extended UVC structure as well as a methodology for automatically generating UVCs to be able to meet all the requirements described above. [DVCON2012] K. Strohmayer and N. Pramstaller, “Holistic Automated Code Generation: No Headache with Last-Minute Changes”, Presented at Design and Verification Conference & Exhibition (DVCon) 2011.

Biography: Klaus Strohmayer is Member of Technical Staff at Dialog Semiconductor. He has more than 13 years of experience in digital design and verification. Prior to joining Dialog Semiconductor in 2008, Klaus was working with Infineon Technologies as digital design and verification expert for the automotive business group. Besides leading the digital design in projects, his main interest is in tooling as well as in design and verification methodologies for complex mixed-signal System-on-Chip Designs.

12:30 EVE - Luc Burgun, CEO and President, Emulation & Verification Engineering S.A
 
Title:  Emulation Prime Time in SoC Design Verification

 
Biography:  Dr. Luc Burgun is President and CEO of EVE, the leader in hardware/software co-verification, and was President of the supervisory board of Cofluent, a leader in ESL specification acquired by Intel in September 2011. Co-founder of EVE, Luc has about 20 years of experience in EDA, where he held engineering and executive positions. Prior to founding EVE, Luc Burgun headed the R&D team of Meta Systems, a wholly owned subsidiary of Mentor Graphics, specialized in hardware emulation systems. He has published numerous articles at international technical conferences and has been granted six patents on accelerated verification. Luc Burgun holds a Ph.D degree in Logic Synthesis from the University of Pierre and Marie Curie, Paris, France.
 
13:00 Lunch and Networking
14:00
Jasper Design Automation - Barbara Jobstmann, Senior Field Applications Engineer
 
Title: Leveraging Formal Verification Throughout the Entire Design Cycle

 
Abstract:  Formal is typically seen as a point tool with limited scope and is usually only applied to a small subset of design and verification challenges. However, with the right supporting technologies and features, the benefits of formal verification can be leveraged throughout all stages including:
 
  • Stand-alone verification of architectural protocols
  • Designer sandbox testing for RTL development
  • End-to-end data packet integrity
  • SoC connectivity and integration verification
  • Root-cause isolation and full proofs during post-silicon debug
 
Traditional verification methods of the above areas are becoming more of a challenge as design complexity increases, but formal verification can be a valuable addition. For example, applying formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about Jasper’s unique formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. We’ll explore new areas that Jasper Formal technologies are addressing including coverage closure, system-level deadlock, low power, and sequential equivalency checking.  When applied intelligently, Jasper formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.
 
Biography:  Barbara Jobstmann is a Senior Field Applications Engineer for Jasper Design Automation. She also holds a researcher position at the French National Research Center (CNRS). Prior to Jasper, Barbara was working in academic research labs in France and Switzerland focusing on constructing correct and reliable systems using formal verification and synthesis techniques.  Barbara holds a PhD in Computer Science from Graz University of Technology, Austria.

 

14:20

Breker Verification Systems Inc - Frederic Krampac, Senior Applications Engineer

Title: Break Your SoC with Automatically Generated C Test Cases

Abstract: SoC teams are finding it impossible to verify a full-chip design from a testbench alone. Inner portions of a large, complex chip are hard to control from the inputs, so deeply buried bugs aren’t discovered until prototyping or final silicon. Since the power of the SoC lies in its embedded processors, many teams write tests to run on the processors in simulation to supplement their testbench verification. However, hand-writing tests takes a great deal of time and effort, rarely resulting in real-world application scenarios or any significant degree of concurrency.

This talk presents an alternative: automatically generated, self-verifying C test cases that run on your SoC’s embedded processors. These test cases try to “break” the SoC with multi-threaded scenarios that represent actual use cases. A high degree of concurrency saturates buses and I/O channels while deviously planned memory allocation looks for overlaps and misalignment. This approach stress-tests every aspect of your SoC design, finds deep bugs in simulation before they escape to silicon, and enables performance measurement under realistic conditions.

Biography: Frederic Krampac is a Senior Applications Engineer at Breker Verification Systems. He has worked on projects involving chip-level integration, IP verification, VIP development, system-level modeling, and software design. Prior to Breker, he was Verification Consultant in the Services group at Synopsys, working for customers worldwide. He has also held EDA engineer positions at Texas Instruments and STMicroelectronics. He holds a degree in Electrical Engineering from Polytech’Montpellier and Politecnico di Torino.

14:40 SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
 
Title:  Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 
Abstract:  Functional qualification – the process of finding weaknesses in and measuring the effectiveness of a verification environment through a fault injection process – has become an accepted and sometimes required aspect of verification since it was pioneered by the Certitude™ product from SpringSoft in 2005.  This unique approach is in daily use by companies worldwide to assess and improve their simulation environments.  The same approach can be applied to formal verification environments.  Given a set of properties, if the RTL functionality is changed through the injection of a fault yet all of the properties still “pass” when proven by a formal verification tool, what does it indicate – a missing property, an incorrectly-described property, an over-constrained environment?  This presentation will explore how functional qualification can be extended to assess and improve formal verification environments to provide a unique perspective on their completeness and correctness.
 
Biography:  Jean-Marc Forey has a degree from the ‘Ecole Nationale Supérieure de Physique de Strasbourg’ (1988). He has held hardware development positions in Thomson CSF, Matra Marconi Space, Philips TRT,
Hewlett-Packard. He has been Senior Verification Application Engineer for Synopsys, then application engineer director in Certess from 2005 until their acquisition by SpringSoft in 2009. Since then he has been Technical Marketing Manager in SpringSoft for Certitude.
 
15:10 Refreshments and Networking
15:40

Cadence - Nick Heaton Senior System and SoC Solutions Architect

Title: The Driving Forces & Industry Innovaton in SoC Analysis and Verification

Abstract: The massive integration of capabilities in mobile devices has produced an explosion in the complexity of the SoCs that drive them. These devices regularly exceed 100 substantial IP blocks and 100+ millions of gates of logic. Multi-core processing is necessary to drive the growth in real-time consumer applications. The number of variables for architecting the SoCs is beyond what can be evaluated statically or with spreadsheets. The industry is exploring how to leap ahead in productivity and to manage the complexity of the system architecture, system development, and system verification.

This talk will cover the leading edge innovations and major industry trends in these areas. From earlier dynamic architectural analysis, software driven verification, through the increasing use of advanced verification automation. The world of verification is rich with innovation!

Biography: Nick Heaton is an ASIC and EDA veteran with more than 25 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honors in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as ARM® and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering. Nick currently works in the Cadence Research & Development organization as a Senior Solutions Architect with special responsibility for Interconnect Verification Automation and Performance Analysis.
 

16:10 Panel Session:  The EDA response
17:00 Concluding Remarks from Platinum Sponsors
(Mentor Graphics, SpringSoft Inc, Cadence, EVE)

 

17:15 Meet the Sponsors in the Exhibition Area
17:45 End of Conference
Participating companies in Windsor include:

Munich, Germany - Agenda
 
Time Agenda
08.30 Arrival: Refreshments and Networking
09.15 Introduction:  Mike Bartley, TVS
09.20 Mentor Graphics - Harry Foster, Chief Scientist
 
Title:   From Paradox to Paradise: Evolving SoC Functional Verification Capabilities

 
Abstract:   A remarkable emergence of new advanced verification techniques, methodologies, languages and new standards has occurred in the past ten years. And recent industry studies have indicated a rapid acceleration in their adoption. This is true across all types of IC design and geographic regions.  Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.
 
Yet for many projects, the process of evolving a team's functional verification capabilities presents a paradox. That is, some projects are unable to quantify the effectiveness of these new processes they put in place—or identify opportunities for process improvement—due to the lack of process measurements. As the saying goes, if you can’t measure it, you can’t improve it.
 
This presentation discusses techniques for evolving your SoC functional verification capabilities, from paradox to paradise, with the introduction of metrics-driven processes. A full set of solutions for managing, analyzing, and automating metrics-driven processes will be described.
 
Biography:   Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored six books on verification--including the 2008 Springer book Creating Assertion-Based IP.  Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
 
10.00 Panel Session: Challenge Papers - Our Top Verification Challenges
  • Infineon – Wolfgang Ecker, Principle Engineer (slides unavailable)
Biography: Wolfgang Ecker is Principal Engineer at Infineon Technologies and Professor at Technical University of Munich. He has 20+ years experience in building and using EDA tools. He received four awards for publications and held many tutorials at various conferences. His research interests are modelling and verification of digital systems at any abstraction level. At the moment, Wolfgang Ecker develops new methods for embedded systems meta modelling.
 
Biography: Martin Ruhwandl studied in electronic design and information technologies at the Technical University in Munich where he also did his PhD (analog simulation techniques). After joining Siemens HL he moved to Infineon where his started his career as functional verification engineer around 12 years ago. With the buy-out of Infineons wireline business in 2009 he joined Lantiq and took over the responsibility of the company wide functional verification methodology.
 
Biography: Michael is design architect within Freescale’s New Product Development Center based in Munich. During his 20+ years with Motorola/Freescale he participated in the development of several SoC’s, system level simulation and design, led process improvement activities, and was one of the architects of Freescale’s common design system as well as the common testbench and device architecture used by the Joint Development Program of Freescale/ST Microelectronics. He is also participating in several standardisation efforts (SystemVerilog IEEE-1800, UVM) and was one of the drivers behind the ISO26262 certification of the MPC5643L device. Now he is concentrating on device architecture, functional safety, verification automation and many other methodology aspects. Michael holds a Dipl.-Inform. from the Technical University of Munich.
 
10.40 Synopsys – Janick Bergeron, Scientist and Fellow
 
Title:  Will everything start to look like a SoC?

 
Abstract:  Recent Mobile and Processor designs show remarkable similarity to each other. Consider the example of the ARM big.LITTLE configuration of A15 and A7 cores, which provide the ability to switch between high-performance and low power, or the Intel Core i7 with its mobile and desktop configurations.
 
With the convergence of these two previously distinct design types, the emerging result looks a lot like an SoC every time and, understandably, the largest and most complex SoCs tend to grab the headlines, but they also drive the verification agenda.
 
The efficiencies and capabilities of verification tools which most benefit SoC designs, are also mighty useful for other types of design, including those more typically found in European design centers, including automotive or industrial designs.
 
To face these challenges in the future, how will the demands of expanding scale and complexity in the midst of shrinking geometries and timescales drive advanced verification technologies into the mainstream? How quickly will ever greater use of complex Interface and bus protocols drive the adoption of Verification IP standardised around SystemVerilog? Can we continue to scale gate-level simulation or will we look to more predictive RTL simulators to find bugs earlier in the design flow? Can high-level static techniques reduce the demands on RTL simulation itself?
 
In fact, when we verify in the future, will everything look like a SoC?
 
In this presentation, Janick Bergeron, Fellow at Synopsys, spreads the verification Tarot to discern the emerging verification technologies, and how unparalleled R&D investment at Synopsys and partnership with leading practitioners is driving several unique technology breakthroughs which will overcome the verification challenges of the near future.
 
Biography:  Janick Bergeron is a Scientist at Synopsys. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models. He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Nortel Networks. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.
 
11.00 Refreshments and Networking
11.30 User Presentations
 
Title:  How to Improve Verification Debugging using DVE
 
Abstract:  Today’s designs and therefore also the testbenches become more complex.  The time spent to debug testbench and design issues is very high. The paper shows how the Synopsys transaction recording built into VCS® and Discovery Visualization Environment (DVE) can be used in SystemVerilog (SV) testbenches.  The paper will also outline an enhanced concept on how to extend the signal based trace driver concept beyond the design border into the testbench transaction level traces.
 
Biography:  Joachim studied electrical engineering at the University of Applied Sciences in Munich, focusing on Data Systems technology.  He has worked for Texas Instruments, Force Computers, Motorola and now works for Freescale as Senior Staff Engineer.  Joachim has presented numerous publications worldwide.
 

Abstract: Designs today include a complex set of power reduction techniques. These techniques are increasingly making their way from the system level down to lower level design entities including IP and block level of an electronic design. These low power techniques have associated functional aspects that must be included in the functional description of the design. The related power scenarios are increasing the overall complexity of the design. Advanced methodologies and associated EDA support are needed to verify the power intent of a design. This presentation briefly addresses the verification requirements of low power design at IP level and discusses few methods and techniques to address those verification requirements.

Biography: François Cerisier has an Engineering Diploma in Digital Signal Processing from Polytech’Sophia, University of Nice-Sophia-Antipolis and over 12 years of experience in verification of IPs, CPUs and System-On-Chips and in hardware/software co-verification. François gained verification methodology expertise from industrial projects of major semiconductor companies (including Infineon, Broadcom, ST-Microelectronics, ST-Ericsson) and EDA startups. He is now leading Test and Verification Solutions subsidiary in France to provide verification services and consulting.

 

Abstract: The ever-growing design complexity remains a key challenge for verification. However, important market requirements such as power or certification must also be addressed to ensure project success. This presentation deals with both present and upcoming challenges, specifically in the area of microcontroller-based ICs.

Biography: Dietmar Heinz studied Mathematics at the University of Augsburg. He started his professional career in central CAD support at Siemens Nixdorf. Later on at Siemens Public Communication Networks he worked on introduction of Emulation as functional verification methodology for ASIC based transmission systems. Today he is responsible for Functional Verification and Verification methodology at Infineon Chip Card and Security ICs.

 

12.30 EVE - Luc Burgun, CEO and President, Emulation and Verification Engineering S.A, EVE.
 
Title:  Emulation Prime Time in SoC Design Verification

 

Abstract: Hardware emulation has been known for well over 20 years.  Originally and during the 90’s it was limited to performing functional verification of the largest designs of the time, namely, CPU and graphics designs.  But starting in early 2000, and gradually until the end of the decade, it moved outside the original niche and developed into a major verification tool for most electronic designs in all markets.

We anticipate that in the next decade it will become the mandatory verification/validation technology for any new embedded design.  This presentation discusses the evolution of hardware emulation, and it highlights features and benefits in its deployment for hardware verification and embedded software validation of System-on-Chips (SOC) designs.

The presentation will conclude with the description of few customer successes in the adoption of hardware emulation.

Biography:  Dr. Luc Burgun is President and CEO of EVE, the leader in hardware/software co-verification, and was President of the supervisory board of Cofluent, a leader in ESL specification acquired by Intel in September 2011. Co-founder of EVE, Luc has about 20 years of experience in EDA, where he held engineering and executive positions. Prior to founding EVE, Luc Burgun headed the R&D team of Meta Systems, a wholly owned subsidiary of Mentor Graphics, specialized in hardware emulation systems. He has published numerous articles at international technical conferences and has been granted six patents on accelerated verification. Luc Burgun holds a Ph.D degree in Logic Synthesis from the University of Pierre and Marie Curie, Paris, France.

13.00 Lunch and Networking
14.00
Jasper Design Automation - Carlo Del Giglio, Staff Field Applications Engineer
 
Title: Leveraging Formal Verification Throughout the Entire Design Cycle

 
Abstract:  Formal is typically seen as a point tool with limited scope and is usually only applied to a small subset of design and verification challenges. However, with the right supporting technologies and features, the benefits of formal verification can be leveraged throughout all stages including:
 
  • Stand-alone verification of architectural protocols
  • Designer sandbox testing for RTL development
  • End-to-end data packet integrity
  • SoC connectivity and integration verification
  • Root-cause isolation and full proofs during post-silicon debug
 
Traditional verification methods of the above areas are becoming more of a challenge as design complexity increases, but formal verification can be a valuable addition. For example, applying formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about Jasper’s unique formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. We’ll explore new areas that Jasper Formal technologies are addressing including coverage closure, system-level deadlock, low power, and sequential equivalency checking.  When applied intelligently, Jasper formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.
 
Biography:  Carlo Del Giglio is a Staff Field Applications Engineer at Jasper Design Automation. He has more than seven years of experience in formal verification. Prior to joining Jasper, he was a senior FAE at OneSpin Solutions. Carlo holds a Master’s degree in Electrical Engineering from the University of Ancona, Italy.
 
14:20

Doulos – John Aynsley, CTO

Title: UVM Now or Never?

Abstract: This presentation highlights the reasons why you should (or in a few cases should not) be adopting UVM right now, and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL.

Biography: John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specialising in VHDL, SystemVerilog, and SystemC. He is co-author of the IEEE 1666-2011 SystemC standard.

14:40

Breker Verification Systems Inc. – Jörg Große, Applications Engineer

Title: Close Your Coverage Loop with Graph-Based Scenario Models

Abstract: SoC teams rely heavily on coverage metrics as a way to gauge verification progress and determine when to tape out. With a constrained-random testbench, test plans track functional coverage closure rather than completion of explicit tests. However, there is no way to definitively close coverage. Biasing inputs, setting constraints, and simply running more tests may increase the chances of hitting coverage, but there’s no guarantee in an open-loop system. The situation is even worse at the full-SoC level, when most teams relay only simple connectivity tests and weak toggle coverage metrics.

This talk discusses the use of graph-based scenario models to both represent SoC functionality and track coverage of all functions and features. These models capture stimulus, expected results, and coverage in a single representation. This enables a true closed-loop coverage system. A verification engineer can simply point to a node of the graph, or a series of nodes that define a path through the graph, and automatically generate a self-verifying C test case that is guaranteed to cover that node or path. The result is a shorter and more predictable verification process and a SoC much more likely to work on first silicon.

Biography: Jörg Große is an Applications Engineer at Breker Verification Systems, Inc. Prior to Breker, he was an independent consultant working on automotive SoC verification and safety qualification. Previously, he was co-founder of Certess Inc., a pioneer in functional fault injection. He has also held positions in ASIC design, verification, and flow automation at Tait Electronics, Motorola, and AMD. He holds a Dipl. Ing. (FH)  from University Anhalt.

15.00 SpringSoft Inc - Jean-Marc Forey, Technical Marketing Manager
 
Title: Applying Functional Qualification to Measure the Effectiveness of Formal Verification Environments

 
Abstract:  Functional qualification – the process of finding weaknesses in and measuring the effectiveness of a verification environment through a fault injection process – has become an accepted and sometimes required aspect of verification since it was pioneered by the Certitude™ product from SpringSoft in 2005.  This unique approach is in daily use by companies worldwide to assess and improve their simulation environments.  The same approach can be applied to formal verification environments.  Given a set of properties, if the RTL functionality is changed through the injection of a fault yet all of the properties still “pass” when proven by a formal verification tool, what does it indicate – a missing property, an incorrectly-described property, an over-constrained environment?  This presentation will explore how functional qualification can be extended to assess and improve formal verification environments to provide a unique perspective on their completeness and correctness.
 
Biography:  Jean-Marc Forey has a degree from the ‘Ecole Nationale Supérieure de Physique de Strasbourg’ (1988). He has held hardware development positions in Thomson CSF, Matra Marconi Space, Philips TRT, Hewlett-Packard. He has been Senior Verification Application Engineer for Synopsys, then application engineer director in Certess from 2005 until their acquisition by SpringSoft in 2009. Since then he has been Technical Marketing Manager in SpringSoft for Certitude.
 
15.30 Refreshments and Networking
16.00 Cadence - Nick Heaton, Senior System and SoC Solutions Architect

Title: The Driving Forces & Industry Innovaton in SoC Aanalysis and Verification

Abstract: The massive integration of capabilities in mobile devices has produced an explosion in the complexity of the SoCs that drive them. These devices regularly exceed 100 substantial IP blocks and 100+ millions of gates of logic. Multi-core processing is necessary to drive the growth in real-time consumer applications. The number of variables for architecting the SoCs is beyond what can be evaluated statically or with spreadsheets. The industry is exploring how to leap ahead in productivity and to manage the complexity of the system architecture, system development, and system verification.

This talk will cover the leading edge innovations and major industry trends in these areas. From earlier dynamic architectural analysis, software driven verification, through the increasing use of advanced verification automation. The world of verification is rich with innovation!

Biography: Nick Heaton is an ASIC and EDA veteran with more than 25 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honors in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as ARM® and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering. Nick currently works in the Cadence Research & Development organization as a Senior Solutions Architect with special responsibility for Interconnect Verification Automation and Performance Analysis.
 

16.30 Panel Session:  The EDA response
17.15

Concluding Remarks from Platinum Sponsors
(Mentor Graphics, SpringSoft Inc, Cadence, EVE)

17.30 Meet the Sponsors in the Exhibition Area
18.00 End of Conference
Participating companies in Munich include:

Sponsors Include:

 

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