Workshop Agenda

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March 14, 2011
Grenoble, France
10:00-18:00


10:00-10:15
Welcome
Adam Morawiec, ECSI

10:15-10:45
Debug Support for Next Generation Automotive Microcontrollers
Albrecht Mayer, Infineon Tecnologies
Abstract:

Automotive microcontrollers are used for complex hard realtime systems in combination with safety and security requirements at lowest possible cost. The debug support architecture for such systems is very challenging since initially it is conflicting with all these points.

This is not a new situation, but the ever increasing integration possibilities due to Moore's law lead to new complexity challenges like multi-core but also new opportunities with now affordable debug logic.
Infineon is the worldwide market leader for automotive semiconductors and has set the debug and automotive measurement standards for powertrain microcontrollers with the current TriCore generation. The debug support architecture with Emulation Devices (ED) and the Multi-Core Debug Solution (MCDS) trigger and trace unit was one reason for this success.

Currently the next generation is being developed based on the gained experiences of automotive suppliers and car manufacturers. This presentation will cover the requirements which confirmed the existing concept with EDs and MCDS, but also new requirements which led to extensions of the concept.

10:45-11:15
Embedded Software Debugging on a Simulated STMicroelectronics Processor RTL Model
Jean-Paul Henriques and Stephane Marmey, STMicroelectronics
Abstract

Considering today’s cost and time to market sensitivity it is important to find and debug functional errors as early as possible and to increase the degree of test and debug automation avoiding the loss of quality, cost and time. Starting software debug early in the project flow, before hardware is available enables higher software quality and shortens the overall design process. This talk will present the usage of a simulated processor RTL model to debug embedded software with a GDB based debugger which is already available for a virtual platform and post silicon debugging. The Incisive Software Extensions (ISX) GDB server interface connects the simulator to the software debuggers available for the target. The paper will present the results of a project at STMicroelectronics, where the universal ISX GDB server implementation was configured for a specific target processor. This debugger interface closed the gap for debugging software during RTL simulation. This creates a seamless debug flow using the same debugger frontend for the whole system development process. Debugging software on simulated RTL model improves code quality and shortens the development time. Additionally, this allows hardware and software developers to use the same debugger environment, which improves communication between these groups.

11:15-11:45
Debugging Trends – Present, Past and Future
Sudharsan Srinivasan and Petri Määttä, Nokia
Abstract:

Debugging software has been well known art and skill for quite some time. With the improvements in mobile technology and mobile platforms and an emphasis towards ultra high performance software systems system level debugging has emerged as one of the most important part of the system design and software development process. In this presentation we analyse the various debugging and tracing techniques, their role in finding performance related issues and thereby improving the performance of the system. In particular we discuss debugging of future SOC given the current trend is towards high Speed (GHz race), SMP, ultralow power and ultra mobile handheld devices with complex CPU and memory architectures. We also discuss how the availability of different system related information enhances the debugging capabilities of the system.

11:45-12:15
Markus Winterholder, Cadence Design Systems

12:15-14:00 Lunch / Demonstrations

14:00-14:30
Debugging System Software with 100s of MIPS and 100% Accuracy
Bill Neifert, Carbon Design Systems
Abstract:

Virtual platforms are playing an increasing important role in the development of complex system on chip designs. The complex nature of system designs however has often dictated the creation of multiple virtual platforms: one platform to execute at 100s of MIPs to enable software development, another platform to perform cycle accurate architectural analysis and often a third platform to combine fast models and accurate models in order to enable firmware development. These multiple platforms have been necessitated by the tradeoff between speed and accuracy inherent in model creation. Unfortunately, this results in a massive validation effort in order to ensure that the platforms are equivalent to themselves and also to the implementation RTL (which is very often yet another representation of the system). More often than not, this forces companies to allocate their scarce resources to the development of a virtual platform which meets only part of their needs. In this presentation, a unified virtual platform will be presented which will enable the creation of a single virtual platform for which can not only run at 100s of MIPS in order to enable software debug but which can also execute with 100% accuracy to enable architectural tradeoffs and firmware development. In addition, to address cases where 100% accuracy is required after billions of cycles have been executed, this platform can also swap from running at 100s of MIPS to 100% accuracy at any software debug breakpoint. A presentation and demonstration will be given.

14:30-15:00
Advanced Formal Methods from Jasper for Post-Silicon Debug Productivity
Carlo del Giglio, Ziyad Hanna, Jasper Design Automation
Abstract:

The majority of currently used post-silicon debug techniques use expensive logic analyzers for observing internal states and external interfaces of the design under test (DUT). The alternative to logic analyzers is to ensure the observability of internal states and traffic with internal on-die debug hooks. This is to enable the entire post-debug process that is composed of three phases:

  • Isolating the failure to a specific block or area (called triage)
  • Finding the cause of the bug
  • Validating the bug fix

Traditional methods applied for post-silicon debug very often show their limits in ability to cope with the real problems: even if the bug is isolated in the triage process, sometimes it is extremely difficult to find the cause of the bug and the sequence of states and inputs that lead to that bug. Currently used methods based on directed random simulation or emulation in many cases may lead to several weeks of bug hunting, as their productivity do not pace with the size of the problem.
This is where the formal methods can significantly improve the situation for two aspects:

  • Time to fix the bug
  • The quality of the fix or workaround

The formal tools Jasper provides, such as ActiveDesign with JasperGold can, starting from the partial failure trace, find the complete trace leading to the bug in the design. And these tools offer a significant advantage over the traditional simulation-based methods of being very fast. The time performance difference can be of days comparing to weeks of work.
The presentation will cover the formal methods support for efficient post-silicon debugging, based on industrial experience and concrete success stories with large SoC companies.

15:00-15:30
Enhanced Package- and Die-Level Defect Localization by Dynamic Lock-In Thermography
Antoine Reverdy, Sector Technologies
Abstract:

Recent improvements of microscopic Lock-In Thermography (LIT) offer the non-destructive localization of thermally active defects like shorts or resistive opens, even through the full package. This paper briefly discusses LIT based analysis flow highlighting benefits of the combination with 3D x-ray. The main focus of the paper is to discuss and demonstrate different ways how to activate the thermally active defects with more complex DUTs / defect signatures, requiring ATE docking.

15:30-16:00 Coffee Break/Demos

16:00-16:30
Using hardware/software co-verification techniques to debug low level Firmware
François Cerisier, EASii-IC
Abstract

In order to allow reduced time-to-market, increased system complexity, design reuse as well as more flexibility, Systems-On-Chips integrate more and more software driven sub-systems (egg: hardware assisted video codec, power management, general control, ...). The features of such processor based subsystems are shared between the hardware implementation itself, the micro-controller being used and its dedicated firmware.

Identifying the root cause of post silicon bugs faces the challenge of tracing the right information between the hardware states and events, and the firmware execution, which nowadays is most of the time impossible due to the high level of constraints of this sub-systems.
However, co-verification techniques and simulation can be used to identify bugs not only pre-silicon, but also post-silicon.

Pre-silicon, these techniques considerably reduces the risk of having major bugs in the hardware implementation or in the firmware flashed in ROM.
Post-silicon, these techniques helps in clearly identifying hardly reproducible bugs by providing a complete trace of both hardware events and software executions without the need complex logical trace analysis or software debuggers

This presentation describes how we have used Cadence ISX Incisive Software eXtension, together with a metric driven verification environment using Cadence Specman to provide extensive pre-silicon verification and debugs as well as to allow post-silicon bug identification.

16:30-17:00
Pat Brouillette, Intel

Presentation via WebEx

17:00-17:30 Discussions / Demonstrations


 

LOCATION
World Trade Center
Centre de Congrès et Seminaire
7 Place Robert Schuman
38000 Grenoble, France
Room: Makalu
(Directions)

 

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