Program Committee

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The 2011 System, Software, SoC and Silicon Debug Conference (S4D)

October 5-6, 2011
Munich, Germany


Conference Chair:

Pat Brouillette, Intel
s4d2011 [at] ecsi [dot] org

Pat Brouillette is a software architect in Intel’s Digital Home Group.  His primary responsibilities are architecture, design, and implementation of embedded media device drivers and firmware.  On the latest SoC’s there are approximately ten million lines of code running on nine processors, from an Atom core to DSPs to several embedded microcontrollers.  To ensure all developers can observe their real-time interactions with hardware and other processing agents, Pat invented the debug instrumentation API called SVEN used by all drivers and embedded processors, and an SoC silicon feature called OMAR which captures 1024 SoC hardware signals simultaneously (See his S4D 2010 paper) giving all software developers in the organization a deep view of failures occurring “in use case.”  Prior to joining Intel pat enjoyed a long career in the creation of broadcast video processing hardware and software, as well as 3D rendering and animation software. Aside from his work, Pat enjoys his family, photography, guitar, piano,  painting, rugby, fly fishing, and several others.


Co-Chair:
Dr. Adam Morawiec, ECSI

s4d2011 [at] ecsi [dot] org
adam [dot] morawiec [at] ecsi [dot] org

Adam Morawiec received his MSc degree in electronic system design in 1993 from the Silesian Technical University in Gliwice, Poland and his DEA (Diplome d'Etudes Approfondies) in 1996 and PhD in 2000 in Microelectronics at the TIMA Laboratory / Université Joseph Fourrier, Grenoble, France in the domain of verification and simulation performance methods.

He works for ECSI in the R&D project development and management in the domain of system design methods and standards, in setting up industry and research consortia, in organisation of advanced training and workshop in system design area. He also acted as an expert of the European Commission in the R&D project proposal evaluation and IST/ICT Work programmes definition. Since 2005 he is the director of ECSI.

He is an author of several scientific publications in the area of formal verification, formal models, simulation performance and system design. He is also an editor of two technical books published by Springer Publishers: “Platform Based Design at the Electronic System Level” and “High-Level Synthesis”.


Steering Committee:
Pat Brouillette, Intel, USA
Albrecht Mayer, Infineon, DE
Adam Morawiec, ECSI, FR
Markus Winterholer, Cadence, DE

Program Committee
Tapani Ahonen, TUT
Sean Baartmans, Intel
Jens Braunes, pls Programmierbare Logik & Systeme GmbH, pls Development Tools
Pat Brouillette, Intel
Al Crouch, Asset-Intertech
Philippe Cuenot, Continental
Serge De Paoli STMicroelectronics
Stylianos Diamantidis Globetech Solutions
Jakob Engblom, Wind River
Philipp Graf, FZIy
Ziyad Hanna, Jasper Design Automation
Andreas Hoffmann, Synopsys
Rohit Kapur, Synopsys
Rolf Kühnis, Intel
Gilbert Laurenti, Texas Instruments
Rainer Leupers, RWTH AACHEN University
Markus Levy, MCA
Andrea Martin, Lauterbach
Albrecht Mayer, Infineon
Klaus McDonald-Maier, University of Essex / UltraSoC
Adam Morawiec, ECSI
Brenden Mullane, University of Limerick
Chris Ng, IBM
Robert Oshana, Freescale
Frédéric Petrot, TIMA Laboratory
Serge Poublan, ARM
Paolo Prinetto, Politecnico di Torino
David Riemens, NXP Semiconductors
Peter Rössler, University of Applied Sciences Technikum Wien
Neal Stollon, HDL Dynamics
Erich Styger, Freescale
Alan P. Su, GCU
Tobias Schwalb, KIT
Thomas Ulber, Mentor Graphics
Bart Vermeulen, NXP Semiconductors
Alexander Weiss, Accemic GmbH & Co. KG
Michael Williams, ARM
Markus Winterholer, Cadence Design Systems
Hans-Joachim Wunderlich, Univeristy of Stuttgart

If you are interesting in joining the S4D 2011 Planning Committee, please contact us at office [at] ecsi [dot] org.

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