Program Committee

Conference Chair: Andrew Swaine, ARM


Andrew Swaine is the CoreSight architect at ARM, responsible for ARM system-level debug and trace technology.  He wrote the industry standard CoreSight architecture, which enables the debug and trace systems of complex SoCs to be built from components implemented by any company, to work together and to be supported by standard tools.  He developed the third-generation ETM architecture, used for processor trace of most ARM processors from the ARM11 family onwards.  He has also led the design of many pieces of debug and trace related IP.  He lives in Cambridge, UK and holds a degree in Computer Science from Cambridge University.



Conference Co-Chair: Adam Morawiec, ECSI


Adam Morawiec received his MSc degree in electronic system design in 1993 from the Silesian Technical University in Gliwice, Poland and his DEA (Diplome d'Etudes Approfondies) in 1996 and PhD in 2000 in Microelectronics at the TIMA Laboratory / Université Joseph Fourrier, Grenoble, France in the domain of verification and simulation performance methods.

He works for ECSI in the R&D project development and management in the domain of system design methods and standards, in setting up industry and research consortia, in organisation of advanced training and workshop in system design area. He also acted as an expert of the European Commission in the R&D project proposal evaluation and IST/ICT Work programmes definition. Since 2005 he is the director of ECSI.

He is an author of several scientific publications in the area of formal verification, formal models, simulation performance and system design. He is also an editor of two technical books published by Springer Publishers: “Platform Based Design at the Electronic System Level” and “High-Level Synthesis”.

Adam [dot] Morawiec [at] ecsi [dot] org


PROGRAM COMMITTEE

  • BAARTMANS Sean – Intel
  • CUENOT Philippe – Continental
  • CROUCH Al - ASSET-Intertech
  • DE PAOLI Serge - STMicroelectronics
  • DIAMANTIDIS Stylianos - Globetech Solutions
  • GRAF Philipp - FZI
  • KAPUR Rohit – Synopsys
  • KÜHNIS Rolf - Nokia
  • LAURENTI Gilbert – Texas Instruments
  • LEUPERS Rainer - RWTH Aachen University
  • LEVY Markus – Multicore Association
  • MARTIN Andrea - Lauterbach
  • MAYER Albrecht - Infineon Technologies
  • McDONALD-MAIER Klaus – U Essex & UltraSoC
  • MORAWIEC Adam - ECSI
  • NG Chris - IBM
  • OSHANA Robert - Freescale
  • POUBLAN Serge - ARM
  • PRINETTO Paolo – Politecnico di Torino
  • RIEMENS David - NXP Semiconductors
  • STOLLON Neal - HDL Dynamics
  • STYGER Erich - Freescale
  • SU Alan P. - Global Unichip Corp / ITRI
  • SWAINE Andrew - ARM
  • VERMEULEN Bart – NXP Semiconductors
  • WINTERHOLER Markus – Cadence
  • WUNDERLICH Hans-Joachim – U Stuttgart