OpenES Consortium

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Consortium Partners:

  • Association: ECSI (France)

 



 

CISC Semiconductor GmbH is a design and consulting service company for industries developing embedded microelectronic systems with extremely short Time-To-Market cycles. Our core competences are: system design, modeling, simulation, verification and optimization of heterogeneous embedded microelectronic systems with a particular focus on Automotive and RFID systems. Our customers are represented in the Semiconductor, Automotive and RFID industry.

Role in the project:
  • Strengthen the system design level aspect focusing on SystemC(-TLM) and other open “standards”
  • Tight integration of requirements, associated tests and simulation (with derived results)
  • Develop and exploit a “light-weight” tool for concept and verification engineering (some focus on ISO262622).

 



Thales is a world leader for mission critical information systems, with activities in some core businesses: aerospace, space, defence, security, ground transportation. It employs 67000 people worldwide and generates revenues of more than € 13 billion. It provides its customers with all the key functions in the critical information loop, from detection and processing to transmission and distribution. The group’s civil and defence businesses develop in parallel to serve a single objective: the security of people, property and nations. More than 20 % of Thales revenues are devoted to R&D with dedicated people and organisation.
Thales develops its strategic capabilities in component, software and system engineering and architectures through its R&T organization. Its six Global Business Units manage their strategy and technical coordination per domain with hundreds of Units in these Divisions developing their technical activities in close relationship with their market. Thales is involved in more than 50 countries for international development and through local partnership with research institutes.
 
Thales Research & Technology
 

Thales Research & Technology (TRT) operates at the corporate level as the technical community network architect, in charge of developing upstream and Thales-wide R&T activities, with vision and visibility. In support of Thales applications, TRT’s mission is to anticipate and speed up technology transfer from research to development in Divisions by developing collaborations in R&T. Thales is international, but Europe-centered with corporate Research and Technology centers in France, the United Kingdom and the Netherlands. R&T activities concentrate on critical information systems, processing, control and cognitive systems.

Role in the project :
The “High Performance Computing” Laboratory involved in this project is part of the Information Science and Technology Group. The experience of the team encompasses parallel architectures design and parallel programming tools. TRT-FR developed an approach for mapping data-streaming application on embedded parallel architectures (rapid prototyping). Both the application and the execution platform are described through a high level modeling. The user can explore various mappings (design space exploration) and automatic parallelization strategies can be performed. This approach also targets virtual prototyping: i.e. how to simulate the application mapped on the execution platform in order to verify its functional behaviour and to evaluate performance. The laboratory is also involved in studies on MDE approaches for heterogeneous multicore embedded systems.
In the OpenES project, TRT intends to:
  • fill the gap between high level application models and hardware platform models: for instance it will consist in both adding more semantics to high level models and extracting low level information (from IPs) to make simulations more accurate
  • consider the multicore mapping for the SDR domain (Rapid prototyping)
  • ease the architecture exploration (Virtual prototyping)

 

Thales Communications & Security

 

Thales Communications & Security (TCS) is a subsidiary of the THALES group and belongs to The Defence & Security C4I Systems Division,  world leader in critical information systems and secure communications. Thales Communications & Security, with 7 000 employees in 14 countries has a solid European base as well as a strong presence in the United States – the world’s largest communications market, in Republic of Korea, Australia, Canada and South Africa.
Digital technologies, mobile communications, integrated services and the integration of multimedia services into communication devices offer new business opportunities and are completely changing the face of Telecommunications. Thales has been one of the driving forces behind these changes, and the features and functions that are now available are already part of the company’s product offering for government agencies and major organizations.

Role in the project:
The main entity of Thales Communications & Security that participates to OpenES is the “Systèmes Numériques Embarqués”, located in Gennevilliers (France). Its mission is to study/provide innovative design solutions for the future Thales radio systems in terms of performances optimization and power consumption, parallelization and portability of the applications on multicore platforms.
TCS is a member of the steering and management committee, leading the workpackage “Enhancement of Design Flows on cases studies” and actively involved in all the other workpackages of the project.

 



DOCEA Power is a privately held company in the Electronic Design Automation field. It was founded in 2006 and has offices in Grenoble (France) and San Jose (US).
Its solutions aim at solving issues related to power consumption and heat dissipation in integrated circuit design, with a prime focus on the specification and early design stages (also designated as the Electronic System Level). In the context of complex circuit design, like the design of Systems-on-Chip and Systems-in-Package, DOCEA’s products enable power and thermal estimation and optimization, while providing a framework to efficiently track data and foster collaboration between stakeholders. DOCEA’s tools are used by semiconductor and electronic equipment manufacturers in market sectors such as wireless, automotive and telecommunication networks, where mastering power consumption and heat dissipation are keys.
As a high tech start-up company DOCEA has a significant experience in creating innovative solutions and setting them up in customer design flows. The R&D team conducts development in the following fields: modeling of power and temperature at architectural level:

  • transition between architectural level modeling and implementation,
  • description of power and thermal management techniques,
  • relation to the resource control and interaction with the software application execution.

DOCEA has also a proven track record as a participant of several European and French collaborative projects. For instance, DOCEA took part in the MEDEA+ project CoSiP (MEDEA+-2T405-CoSiP) to develop thermal modeling in a chip-package-board co-design flow, and it interfaced power and thermal estimation with SystemC-TLM simulation in the French ANR program HeLP (ANR-09-SEGI-006).

Role in the project:

Docea will bring its support to integrate its contribution in the project into the targeted design flow.

  • Representation of power and thermal estimation on the system level view : power consumption budget per use profile and system function as well as identification of temperature-critical profiles and functions
  • Definition of the conditions related to power and temperature in the use case description
  • Definition of the modeling needs for architectural power and thermal analysis
  • Definition of the power and thermal target budgets and implementation of the related validation functions
  • Implementation of the verification functions
  • Support for deployment and integration
  • Specific actions to standardization efforts
  • Publications related to case studies applying the developed design flow.

 




Vector Fabrics specializes in developing tools for the design and implementation of multicore, multi-threaded applications and embedded systems. The management team brings over 100 years of combined experience in both large companies and startups in Europe and the United States. As pioneers we have embarked on the road to deliver tools that eliminate the manual work when it comes to optimizing software for multicore architectures. As innovators we have provided the industry with proven tools that solve the multicore programming challenge. Our tools empower software engineers to fully utilize and harvest the ultra-high performance that parallel architectures provide, allowing them to bring a great user experience to their customers. We believe in our vision, we are passionate about our customers and believe in quality, both in the people we hire and the tools we create.
 
Role in the project:
Vector Fabrics current software tools focus on application-analysis for multi-core processor systems, relying on the homogeneous cache-coherent properties of mainstream multi-core architectures from e.g. Intel and ARM. To extend the capabilities towards requirements posed by subsystem design, two major innovation aspects must be covered:
  • The targeted subsystems are driven through a software interface, to be defined as an API and a low-level interface, characterized by memory maps and interrupts. Adding performance characteristics on such interfaces, mostly by analyzing the subsystem software, is a novel and challenging objective.
  • The proposed subsystems have more specialized multi-core architectures for HW cost and power advantages, which incurs significant software complexities. In this project the mapping of software to such non-coherent architectures will be studied in order to handle these complexities.

 



The Eindhoven University of Technology (TUE) was established in 1956, and is ranked among the top universities in Europe. TUE is a worldwide leader in industry-university cooperation, and the Eindhoven region was elected by the Intelligent Community Forum as the most intelligent region in the world in 2011. The Electronic Systems (ES) group has expertise on (formal) modelling and design of embedded systems. ES is involved in many (inter)national projects relating to intelligent, ubiquitous, real-time embedded (multimedia) systems, and wireless sensor networks. Major research themes are multiprocessor systems on a chip, networks on chip, real-time embedded systems, models of computation, trade-off analysis, multi-objective optimization, synthesis trajectories, resource management and scenario-based design. The ES group has strong links with European and Dutch industries, including the semiconductor industry, with partners at different positions in the value chain (manufacturing, IP houses, system houses, EDA tooling, and applications), consumer electronics, personnel and institutional health care.

Role in the project:
In the OpenES project, TUE will work on recent embedded systems that run multiple virtualized applications simultaneously, with time and energy budgets per application. In this project we will contribute to the modelling the requirements of these applications. In addition, we will contribute to the modelling of the virtual processors offered by the hardware & software platform (e.g. application time & energy budgets, arbiter settings for hardware and software schedulers, the associated software drivers, and the per-application task schedulers and power-managers).

 



Verimag, created in 1993, is an academic research laboratory affiliated with University Joseph Fourier (UJF - Grenoble 1), the National Center for Scientific Research (CNRS/INS2I) and Grenoble Institute of Technology (Grenoble INP).
Research at Verimag provides theoretical and technical means for developing embedded systems, contributing to scientific advancement and industrial progress. Over the last fifteen years, Verimag has actively contributed to the development of the state-of-the-art, in particular for synchronous languages, verification, testing and modeling.
The tools produced at Verimag are regularly transferred to commercial CASE tools and are used in a number of industrial applications.
Verimag's strategy is to maintain a good balance between fundamental, experimental and applied research. This is particularly visible in long term cooperation with academic and industrial partners.

Role in the project:
Verimag will contribute to a well-defined structure for high-level models of individual components, subsystems, or full systems. The structure will include both the functional behavior and extra-functional properties like timing and energy consumption. Verimag will work in two complementary directions: 
  • A formal definition, independent of any particular modeling language/simulation engine, and including a notion of functional- and  extra-functional contracts for hierarchic HW/SW component-based systems
  • An efficient execution engine based on SystemC, and able to run the simulation in parallel on multi-core host machines.

 



Magillem provides to customers in the electronic industry tools and services that drastically reduce the global cost of complex design. Capitalizing from its strong experience in the integration of intellectual property blocks on the semi-conductors assembly platforms, Magillem is deploying its solution towards systems integrators. Magillem enables the deployment of solutions using the IP-XACT IEEE1685 description standard; it offers the capacity to precisely describe all the components and tools used in the production chain. Magillem brings, in a non-intrusive way for the existing flow, the concept of communication backbone by integrating “business objects” used all along the flow. Data specific to tools and components are integrated as metadata in the IEEE specifications open standard. This solution is a true revolution in the management of the electronics chain since it allows a manufacturer to handle its design flow independently from proprietary formats attached to the tools used in the flow.

Role in the project:

Magillem will bring the requirements related to the specification of the hardware structure (IP-XACT) in the global system architecture (several formats are envisaged). Links have to be done between the system engineering with specification levels and the hardware modeling and implementation levels. The target is to specify the requirements for the modeling kit to ensure correspondences between the several aspects of hardware related specifications and the several implementation levels.

Magillem will also study and propose techniques and mechanisms to automate the generation/aggregation of code for models building using higher specification levels. The modeling (using UML) of documentation with MRU (Minimum Reusable Unit) will be the basis of our contribution.

Finally, Magillem will develop the engines dedicated to the verification of assembly; the challenge here is to consider complex assemblies of components or subsystems and detect errors of functional type by launching tests, verifying rules, or interoperate several verification flows. The validation will be done by comparing the specifications expressed at the system level with the actual properties of the composite virtual prototype; this will have to be done through the hierarchy (subsystems, IPs); basic validation just stating yes/no will be enhanced with capability to report information on how the implementation deviates from the specification.

 



STMicroelectronics is an independent worldwide broad-range semiconductor supplier and it is ranked in the top ten semiconductor companies in the world with over 53,000 employees. ST aims at becoming the undisputed leader in multimedia convergence and power applications, dedicating significant resources to product innovation and increasingly becoming a solution provider. In digital consumer applications ST has had considerable success, ranked number one for MPEG2 decoder devices sales (over 600M devices shipped to date), and achieving leading market share for digital satellite, cable and internet Set Top Box (STB) devices. Its Grenoble centre has played a driving role in the design and development of STB and TV products for the last ten years, recently introducing dual HD decode and 3D Graphics on the same die.

Role in the project:
In OpenES, ST is project coordinator, WP1 package leader and is involved in the various facets of the project, from requirements down to experimentation on case studies, through development of corresponding technologies.

 



NXP Semiconductors N.V. (NASDAQ: NXPI)  creates solutions that enable secure connections for a smarter world. Building on its expertise in High Performance Mixed Signal electronics, NXP is driving innovation in the automotive, identification and mobile industries, and in application areas including wireless infrastructure, lighting, healthcare, industrial, consumer tech and computing. NXP has operations in more than 25 countries, and posted revenue of $4.36 billion in 2012. Additional information can be found by visiting www.nxp.com.
The NXP Corporate Innovation & Technology department responsible for the Design Technology & Flows will participate in the OpenES project. The involved department focuses on System Level Design and Verification for AMS Systems and was involved in many EU projects like Scalopes, SPRINT, Verdi.

Role in the project:
The contribution of NXP to the OpenES project will focus on System Level modeling and verification of mixed analogue-digital  IC’s.
One focus point will be on requirements management. In IC development projects it is key that the created designs adhere to the (in practice constantly changing) customer requirements. Consistent management of requirements and their related tests is needed in order to create first time right designs.
Second point of focus is on verification/simulation of combined analogue/digital systems. Currently many products contain both digital and analogue parts that are tightly interacting with each other (digital assisted analogue). Simulation of such a mixed signal system is needed for verification. To circumvent simulation times of weeks, abstract modeling of analogue circuits is needed.

 




Synopsys, Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys' comprehensive, integrated portfolio of system-level, IP, implementation, verification, manufacturing, optical and field-programmable gate array (FPGA) solutions help address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk. For more than 25 years, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems.  The company is headquartered in Mountain View, California, and has approximately 90 offices located throughout North America, Europe, Japan, Asia and India. More information can be found on www.synopsys.com.

 Synopsys Netherlands participating in OpenES is part of the Solutions Group (SG) of Synopsys, which provides high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare® IP portfolio includes complete interface IP solutions for widely used protocols, analog IP, embedded memories, logic libraries, SoC infrastructure IP, processor IP and IP subsystems. In addition, the Solutions Group offers SystemC tooling and transaction-level models to build virtual prototypes for rapid, pre-silicon development of software and architecture exploration. The Synopsys Netherlands R&D centre develops new HW/SW subsystem IP, such as high-quality multi-channel audio subsystems.

Role in the project:
Synopsys Netherlands aims to bring its (sub-)system integration knowledge to the project. The contribution of Synopsys to the OpenES project will focus on the modelling of subsystems in order to facilitate their development, exchange, configuration and integration. This will include the modelling of so-called non-functional aspects, such as performance and power characteristics. It will further include the modelling of software interfaces that are used to interact with subsystems. Synopsys is also acting as work package leader for WP2.

 

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