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FDL 2015
Forum on specification & Design Languages
September 14-16
Barcelona, Spain


FDL 2015 Program

Monday, September 14

13:30-14:25  Registration
14:25-14:30  Welcome 
14:30-15:30  Keynote 1 : Jesus LABARTA, University of Catalonia, Spain
Chair: Julio Medina
Task Based Parallel Programming in HPC and beyond
15:30-16:00  Coffee break
16:00-17:30  Session 1 : Clocks and their Applications
Chair : Ashraf Shalem
Co-chair: Franco Fummi
17:30-18:30  WiP and other contributions
18:30-20:00  Demo Night & Poster Presentations
Chair: Carles Hernandez
Co-chairs: Rolf Drechsler, Adam Morawiec


Tuesday, September 15

09:00-10:00  Keynote 2 : Franco Fummi, University of Verona, Italy
Chair: Rolf Drechsler
Co-chair: Dominique Borrione
 The Babel of Languages in Smart Systems Design
10:00-10:30  Coffee break
10:30-12:30  Special Session 1 : Power Aware Modelling and Design
Chair: Javier Moreno Molina
12:30-14:00  Lunch
14:00-15:30  Session 2 : FMI and SystemC-AMS
Chair: Franco Fummi
Co-chair: Rolf Drechsler
15:30-16:00  Coffee Break
16:00-17:30  Session 3 : Design and Correctness
Chair: Dominique Borrione
Co-chair: Ashraf Shalem
17:30-22:00  Social Event


Wednesday, September 16

09:00-10:00  Session 4 : From MARTE models to initial implementations
Chair: Fernando Herrera
Co-chair: Kim Grüttner
10:00-10:30  Coffee Break
10:30-12:30  Special Session 2 : High Integrity Multi-Core Modelling for Future Systems (Hi-MCM) 
Chair: Kim Grüttner
12:30-14:00  Lunch
14:00-16:00  Special Session 3 : Towards Analog-/Mixed-Signal Coverage
Chair: Lars Hedrich, Gregor Nitsche
16:00-16:15  Closing

Monday, September 14
13:30-14:25  Registration
14:25-14:30  Welcome 
14:30-15:30  Keynote 1 : Jesus Labarta
Task Based Parallel Programming in HPC and beyond
Abstract : The talk will present a vision how multicore architectures are impacting parallel programming practices in the high performance context.

Using the OmpSs programming model developed at BSC as a conductor, we will show how we think the challenges new architectures are posing should be addressed.

Overal, key ideas of our vision are to provide a clean interface to the programmer that decouples her from the architecture itself and lets her focus on the algorithmic issues, data accesses and dependences. We advocate for intelligent runtimes to take the responsibility of  mapping the computations expressed by the programmer to the available resources in a potentially very dynamic environment.

We aim at OmpSs being a forerunner for OpenMP, proposing and experimenting with features that we believe should be included in such model aiming not only at HPC but also at all kinds of general purpose computing. Example features we will briefly describe include the asynchronous data flow execution of tasks, the support for heterogeneous devices such as GPUs or systems with big and little cores, the benefits of automatic locality aware scheduling policies and hybrid MPI+OmpSs programming.

15:30-16:00  Coffee break
16:00-17:30  Session 1 : Clocks and their Applications
 This session presents a new technique to verify synchronization protocols on RTL designs that automatically extract synchronizers from a flat design, and helps to formally verify the correctness of the implemented synchronization protocol. It also present an approach to dynamically tune the time quantum in temporally decoupled simulations in order to improve the accuracy/performance tradeoff in virtual prototypes. Finally it presents an approach for the high level modeling of efficient power strategies in ESL design, which helps analyzing the effect of clock gating and frequency scaling by using a template that allows to integrate clock domains in SystemC-TLM simulations with power management support.

Enabler-Based Synchronizer Model for Clock Domain Crossing static Verification
Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone and Dominique Borrione
Temporal Decoupling with Error-Bounded Predictive Quantum Control
Georg Gläser, Gregor Nitsche and Eckhard Hennig
A Methodology for inserting Clock-Management strategies in Transaction-Level Models of System-on-Chips
Hend Affes, Michel Auguin, Francois Verdier and Alain Pegatoquet

17:30-18:30  WiP and other contributions
18:30-20:00 Demo Night & Poster Presentations
The Forum on Specification and Design Languages invite all FDL attendees to enjoy with us this demonstration + poster session and a reception

The Demo Night session and reception is free of charge for all FDL attendees!

A Coverage Adoption For A Direct Testing
Sameh El-Ashry and Khaled Salah

Accelerating Coverage Collection for Mixed-Signal Systems in a UVM Environment
Sebastian Simon, Georg Pelz and Linus Maurer

Clock Management and Analysis for Transaction-Level Virtual Prototypes
Amal Ben Ameur, Hend Affes, Michel Auguin and Francois Verdier

Fault-Injection Techniques for TLM-Based Virtual Prototypes
Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Kai Liu, Nadereh Hatami,Andreas von Schwerin and Hendrik Post

An Integrated Framework for Model-Based Design and Analysis of Automotive Multi-Core Systems
Khalid Latif, Charles Effiong, Abdoulaye Gamatie, Gilles Sassatelli, Leonardo Zordan, Luciano Ost, Piotr Dziurzanski and Leandro Indrusiak

Timing Correction Technique for Fast and Accurate State-Based Performance Models
Sebastien Le Nours

Towards Certification-aware Fault Injection Methodologies Using Virtual Prototypes
Jaime Espinosa, David De Andrés, Juan Carlos Ruiz, Carles Hernandez and Jaume Abella

Security Services for Mixed-Criticality Systems based on Networked Multi-Core Chips
Thomas Koller and Donatus Weber

Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware
Fatemeh Javaheri, Katell Morin-Allory and Dominique Borrione

Multi-threaded Virtual Platform Simulation: An open-source approach, using SystemC TLM-2.0, and QEMU
Guillaume Delbergue, Mark Burton, Bertrand Le Gal and Christophe Jego

Beyond QBox: development of virtual platforms based on QEMU and SystemC TLM-2.0
Guillaume Delbergue, Mark Burton, Christophe Jego and Bertrand Le Gal

Schedulability analysis and optimization in a model-based integrated tool-chain
Laurent Rioux, Rafik Henia, Nicolas Sordon, Michael González Harbour, J. Javier Gutiérrez, Juan M. Rivas, César Cuevas, Jose M. Drake and Julio Medina

Tuesday, September 15

09:00-10:00  Keynote 2 : Franco Fummi
 The Babel of Languages in Smart Systems Design
Abstract : Smart systems are a tight integration on a chip of highly heterogeneous components, ranging from analog and digital hardware to MEMs, sensors and actuator, power sources and devices, network transceivers and, finally, embedded software.

All such components must be modeled, designed and validated by specialized teams that must use their favorite design languages. An Esperanto for all such design domains is a chimera, thus we have to deal with a Babel of languages and the speech summarizes the main modeling, design and validation problems, by proposing techniques to reduce this heterogeneity to an homogeneous abstracted representation, particularly effective for validation and connected to design activities. A complete design example will be also introduced, to give to everybody the possibility to make practical experiments in this attractive and challenging field.

10:00-10:30  Coffee break
10:30-12:30  Special Session 1 : Power Aware Modelling and Design
 This special session will explore the different constraints in power aware design as well as different modelling approaches to overcome them. The session will start with a system level power consumption modelling approach that enables the simulation of power consumption transients and their effects on AMS subsystems. The next presentation will introduce a model to estimate and benchmark wireless sensor nodes energy lifetime, including power consumption and battery models. The third presentation will show an approach to measure energy and power consumption in multi-core Systems-on-Chip in order to optimise software. Finally the last presentation will analyse near-threshold logic circuits and its vulnerabilities and will propose models of error-aware logic circuits. 

Modeling Power Consumption at System-Level for Design of Power
Integrity-Aware AMS-Circuits
Xiao Pan, Javier Moreno and Christoph Grimm.
WiSeBat: Accurate Energy Benchmarking of Wireless Sensor Networks
Quentin Bramas, Wilfried Dron, Mariem Ben Fadhl, Khalil Hachicha, Patrick Garda and Sebastien Tixeuil
Fine-grained Energy/Power Instrumentation for Software-level  Efficiency Optimization
David Greaves, Milos Puzovic, Ali Mustafa Zaidi, Klaus McDonald-Maier and Andrew Hopkins

12:30-14:00  Lunch
14:00-15:30 Session 2 : FMI and SystemC-AMS
This session presents an approach to connect multiple System-C virtual platforms via the Functional Mock-Up Interface (FMI), allowing co-simulations of complex systems consisting of many Functional Mock-Up Units (FMUs). It also presents a methodology to generate these FMUs from SystemC/SystemC-AMS to represent electronics systems for an automotive simulation environment. Finally it introduces a new method to design conservative behavioral models of AMS blocks in SystemC AMS by translating a Verilog-AMS model into a netlist of SysetmC-AMS/ELN primitives.

Virtual Hardware-In-The-Loop Co-Simulation for Multi-Domain
Automotive Systems via the Functional Mock-Up Interface
Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler and Andreas Hoffmann.
Standard Compliant Co-Simulation Models for Verification of Automotive Embedded Systems
Martin Krammer, Helmut Martin, Zoran Radmilovic, Simon Erker and Michael Karner.
Conservative Behavioural Modelling in SystemC-AMS
Sara Vinco, Michele Lora and Mark Zwolinski

15:30-16:00  Coffee Break
16:00-17:30 Session 3 : Design and Correctness
 This session presents a domain-specific language for high-level synthesis of hardware for FPGA platforms and describes its memory management for pipelined target architectures. It also presents a methodology to construct test sequences starting from PSL assertions and design under test written in VHDL using VSYML and SyntHorus tools.

Finally it presents a top-down design flow to refine an architecture level description of a system into an RTL implementation, while refining operation properties concurrently.

A Special-Purpose Language for Implementing Pipelined FPGA-based Accelerators
Cristiano Bacelar De Oliveira, Ricardo Menotti, Joao Cardoso and Eduardo Marques
Towards a Toolchain for Assertion-Driven Test Sequence Generation
Laurence Pierre
Architectural System Modeling for Correct-by-Construction RTL Design
Joakim Urdahl, Dominik Stoffel and Wolfgang Kunz

17:30-22:00  Social Event

Wednesday, September 16

Session 4 : From MARTE models to initial implementations
This session presents a proposal of elements for the specialization of the UML profile for MARTE dedicated to networks and distributed embedded systems. It also presents a model-based approach to the problem of dynamically reprogramming an FPGA. By using model-based methods, characterized by high-level specifications, and automated code generation, developers are protected from worrying about low-level and vendor-specific details required for FPGA reprogramming.

Extensions to the UML Profile for MARTE for Distributed Embedded Systems
Emad Samuel Malki Ebeid, Julio Medina, Davide Quaglia and Franco Fummi
Building a Dynamically Reconfigurable System Through a High-Level Development Flow
David de La Fuente, Jesús Barba, Juan Carlos López, Xerach Peña, Pablo Peñil and Pablo Sanchez

10:00-10:30  Coffee Break
10:30-12:30 Special Session 2 : High Integrity Multi-Core Modelling for Future Systems (Hi-MCM) 
 Modern embedded applications already integrate a multitude of functionalities with potentially different criticality levels into a single system. Driven by the availability of embedded multi-core System-on-Chips, this trend is expected to grow in the near future. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs.

The Assurance of Multi-Core and Mixed Criticality Systems is an ongoing challenge for high integrity and safety critical development, which will be addressed in this session. The first talk proposes an executable system model for functional simulation enabling the observation of dynamic effects caused by mixed-criticality mode switching. The proposed model allows the expression of dynamic execution modes and execution time estimates for each criticality level. The second talk presents how to integrate formally based models relying on the Synchronous Dataflow Model-of-Computation within a component-based application model captured in a UML/MARTE extension suitable to express extra-functional properties and criticality levels. The third contribution is an IEC-61508 compliant validation strategy of the temporal independence on a partitioned multicore mixed-criticality system and presents evidences through a set of performed measurements. This session closes with a user experience report on the applicability of UML/MARTE in an automotive battery management system, considering functional and extra-functional properties.

Mixed-Criticality System Modelling with Dynamic Execution ModeSwitching
Philipp Ittershagen, Kim Gruettner and Wolfgang Nebel
Enhancing Analyzability and Time Predictability in UML/MARTE Component-based Application Models
Fernando Herrera, Pablo Peñil and Eugenio Villar
Temporal Independence Validation for IEC-61508 compliant Mixed-Criticality Systems based on Multicore Partitioning
Asier Larrucea Ortube, Irune Agirre, Carlos Fernando Nicolas, Jon Perez, Mikel Azkarate-Askasua and Ton Trapman
A Novel Design Method for Automotive Safety-Critical Systems based on UML/MARTE.
Ralph Weissnegger, Markus Pistauer, Christian Kreiner, Kay Roemer and Christian Steger

12:30-14:00  Lunch
14:00-16:00  Special Session 3 : Towards Analog-/Mixed-Signal Coverage
 Analog-/Mixed-Signal (AMS) design verification is one of the most challenging and time consuming tasks of today’s complex heterogeneous chip designs. Consequently, there is an urgent demand for deciding whether an AMS design is sufficiently tested or verified.

For software and digital design several Coverage Metrics are already well known to quantitatively evaluate the amount of the invested verification effort. Not being directly applicable for AMS circuits and systems, new methods and metrics are necessary to enable such quantitative evaluations for also the AMS verification progress. In the ANCONA (ANalog COverage in NAnoelectronics) project the consortium is working towards concepts and practical solutions for measuring AMS coverage and supporting AMS coverage analysis within reliable and efficient verification methods.

This special session aims at initiating and strengthening the discussion about AMS coverage, presenting first research findings and approaches of the ANCONA project partners. In the first talk, the challenges of AMS coverage and the consortium’s approaches towards new AMS coverage metrics will be outlined. The second presentation shows an approach to evaluate the AMS coverage based on a discretization of the system’s AMS state space. The third talk presents an approach of symbolically representing and simulating the uncertainties of an AMS system model abstraction, enabling the Validation and Verification with a measurable coverage. The fourth contribution shows, how AMS simulations can be massively speeded-up by avoiding numerical integration and using piecewise-linear modeling for the analog part of the system. The fifth talk presents an approach for the systematic annotation of AMS properties to existing SystemC models, aiming to identify and to verify critical scenarios by a coverage-oriented procedure. The session closes with a proposal for a contract based coverage analysis and AMS contracts, extending contract based design to the specification, verification and coverage evaluation of AMS systems.

AMS-/EF-Contracts – A Discussion of Contracts for AMS-Verification and AMS-Coverage-Analysis
Gregor Nitsche
Automatic Annotation of Properties to ESL SystemC Models and Accelerated Simulation
Georg Gläser and Eckhard Hennig
Detecting Design Flaws using Analog State Space Coverage
Andreas Fürtig
Analog Mixed-Level Modeling for Accelerated Simulation to Increase the Analog Coverage
Hyun-Sek Lukas Lee, Markus Olbrich and Erich Barke

16:00-16:15  Closing


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