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FDL 2014
Forum on specification & Design Languages

October 14-16, 2014
Munich, Germany
 

FDL 2014 Program(pdf)
Click on the links in the table to see the descriptions of the sessions.
 

Tuesday, October 14

10:00-11:00  Registration
11:00-11:25  Welcome Coffee
11:25-11:30  Welcome to FDL
11:30-13:00  Formal Models & Verification *
13:00-14:00  Lunch
14:00-15:30  Predictability*
15:30-16:00  Coffee Break
16:00-17:00  SystemC Modeling and Simulation
17:00-17:30  Work-in-Progress session
17:30-20:00  Demo Night + WiP Posters   &   FDL  Reception

* Sessions with best paper candidates
 

Wednesday, October 15

09:00-10:00  Keynote 1: Bernd Adler, Intel Mobile Communications
10:00-11:00  Parallel Simulation and Verification
11:00-11:30  Coffee Break
11:30-13:00  Requirements *
13:00-14:00  Lunch
14:00-15:30   Panel: Requirements for future AMS design support
15:30-16:00  Coffee Break
16:00-17:30  Parallel Architectures *
18:00-22:00  Social Event

* Sessions with best paper candidates


Thursday, October 16

09:00-10:00  Keynote 2: Bert Dexters, Flanders' DRIVE
10:00-10:30  Coffee Break
10:30-12:30  A Tutorial on Using UVM for Analog/Mixed-Signal Verification
12:30-14:00  Lunch
14:00-15:30  Special Session: Natural Language Processing for Requirements
 Formalization
15:30-16:00  Coffee Break
16:00-17:30  Power
17:30-17:45  Closing

Rooms:

Regular sessions: Reger/Orff/von Weber

Lunch: Foyer Strauss & Hilton Corridor

Demo Night + Poster & Reception: Reger/Orff/von Weber + Foyer Strauss & Hilton Corridor

Keynote 1: Ballroom Strauss A+B

FDL TPC Meeting: TBD
 

 

Tuesday, October 14

 

10:00-11:00

 

Registration

 

11:00-11:25

Welcome Coffee

 

11:25-11:30

Welcome to FDL

General Chair
Frank Oppenheimer, OFFIS

 

11:30-13:00

Formal models & Verification 

Chair: Gjalt de Jong, ArchWorks

Abstract:
This session of three papers addresses the various forms of consistency checking in model based engineering. Within model based engineering, systems are modelled from different views. A different formalism is often used for each perspective, and those models then need to be internally consistent in order for a correct and effectively realizable design. The first paper covers the incremental refinement of a system’s functionality using class diagrams, whereas the second paper then checks the consistency of a system’s behavioral view and it’s structural definition. The third paper then derives a complete interface specification from a partial one in order to support the modeler needs. A common theme between the three papers is also the use of Satisfiability Modulo Theories (SMT) checkers to assist in the practical verification of the methods.

Automatic Refinement Checking for Formal System Models
(Best Paper Candidate)
Julia Seiter, Robert Wille, Ulrich Kühne and Rolf Drechsler

Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kuehne and Rolf Drechsler

Verification of Unit and Dimensional Consistencies in Polychronous Specifications
Mahesh Nanjundappa and Sandeep Shukla

 

13:00-14:00

Lunch

 

14:00-15:30

Predictability

Chair: Julio Medina, Universidad de Cantabria

Abstract:
This session addresses predictability in the behavior of embedded systems in several ways. The first paper proposes a SystemC based modeling and simulation framework for time-triggered safety-critical embedded systems. The second one presents a methodology to model analog faults on the behavioral level to evaluate safety goal violations in automotive systems. Finally, the third paper presents a SystemC-based modelling and analysis infrastructure for high-level, static and simulation-based analysis for timing predictability that enables design space exploration.

A novel modeling framework for time-triggered safety-critical embedded systems
Iban Ayestaran, Carlos F. Nicolas, Jon Perez, Asier Larrucea Ortube and Peter Puschner

Towards Simulation Based Evaluation of Safety Goal Violations in Automotive Systems
(Best Paper Candidate)
Oezlem Karaca, Jerome Kirscher, Linus Maurer and Georg Pelz

An Extensible Infrastructure for Modeling and Time Analysis of Predictable Embedded Systems
Fernando Herrera and Ingo Sander

 

15:30-16:00

Coffee Break

 

16:00-17:00

SystemC Modelling and Simulation

Chair: Philipp A. Hartmann, OFFIS
Co-Chair: Fernando Herrera, Universidad de Cantabria

Abstract:
SystemC has been proven as a strong technology for heterogeneous system modelling, efficient simulation, static and dynamic analysis, and model transformation fostering the needs for design validation and design space exploration. The first paper in this session describes a SystemC-based framework for modeling communication at different layers using SystemC AMS and TLM extensions, demonstrated by a Bluetooth Low Energy case study. The second paper addresses the problem of data races in parallel systems. A dynamic data race detection approach for SystemC/TLM based on a combination of the lockset and happens-before algorithms is presented, which supports precompiled IP models through dynamic binary instrumentation.

Hybrid Dynamic Data Race Detection in SystemC
Alper Sen and Onder Kalaci

Multi-Level Modeling of Wireless Embedded Systems
Fangyan Li, Eric Dekneuvel, Gilles Jacquemod, Davide Quaglia, Michele Lora, François Pêcheux and Rémi Butaud

 

17:00-17:30

Work-in-Progress papers presentation

Chair: Frank Oppenheimer, OFFIS
Co-Chair: Julio Medina, Universidad de Cantabria

Abstract:
The WiP session aims to present innovative ideas which are - though not fully mature - able to inspire new ideas and to stimulate controversial discussions. The first paper proposes an API for annotating and monitoring power and energy in system level design models. It addresses heterogeneous designs and claims to be very flexible and thus applicable to various SLDL (e.g. SpecC or SystemC). The second paper addresses the important problem of bringing a from 'black-board level' design idea to a first executable specification. It does so be applying an ontology based reusable modelling library for IP components that assists refinement of vague ideas or incomplete specifications.

PowerMonitor: a Versatile API for Automated Power-Aware ESL Design
Yasaman Samei and Rainer Dömer)

A Concept for Design of Embedded Systems at Semantic Level
Frank Wawrzik, Javier Moreno and Christoph Grimm

 

17:30-20:00
Demo Night
 

The Forum on Specification and Design Languages invite all FDL attendees to enjoy with us this demonstration + poster session and a reception

The Demo Night session and reception is free of charge!

Room: Foyer Strauss & Corridor

 

Wednesday, October 15

 

09:00-10:00

Keynote 1

Bernd Adler, Intel Mobile Communications

Speaker: Bernd Adler, Intel Mobile Communications

Abstract:
The development of advanced mobile communication and multimedia devices face unprecedented challenges. “Internet of Things”, “Smart Everything”, or “Everything connected” are the new buzzwords characterizing future applications. Their cornerstone will be highly integrated System-on-Chip (SoC) solutions offering a wide range of features at lowest costs and minimal energy consumption. These advanced SoCs cannot be mastered without an end-to-end optimization of the entire development process with improved EDA standards, methodologies and tools. Advanced system features result in a skyrocketing complexity of firmware and software. At the same time, the innovation cycles are constantly shrinking. These contradicting requirements can only be reconciled through a dramatically increased development efficiency.
Today’s system and software development is based on virtual prototyping, enabling early feature development where hardware and software can evolve together, including investigations on different system architectures. In addition, silicon, package and printed circuit board need to be developed concurrently to meet the requirements of simultaneously active communication technologies, without sacrificing an optimum system cost position. The final system integration and verification is not possible without extremely high technical expertise and a close collaboration across the entire system.
This keynote will cover: 1) the change in system properties, 2) the evolution in product development and their challenges, and 3) the requirements for the next generation EDA standards, tools and solutions.

Bio:
Bernd has held the position of RF Chief Scientist and Head of Wireless System Engineering at Intel® Mobile Communications Group Wireless System Engineering activities engineering, line management, product management and site management positions at Infineon Technologies for over 12 years working on cellular transceivers for CDMA, WCDMA, WIMAX and LTE as well as 2G monolithic integration activities paving the way to ultra low cost products. Before this he held RF engineering positions working on modules and oscillators for Base stations. He received his diploma (electrical engineering) in 1989.

 

10:00-11:00

Parallel Simulation and Verification

Chair: Fernando Herrera, Universidad de Cantabria
Co-Chair: Philipp A. Hartmann, OFFIS

Abstract:
In this session, the first paper presents a contribution which can be used to easily create customized portfolio solvers. Specifically, the metaSMT framework is extended with a SMT-LIB2 parser and a TCP server/client architecture, which allows for deciding SMT instances simultaneously with multiple solvers. The second paper makes an structured presentation of different parallel SystemC simulation approaches at the register transfer level, and shows how the selection of the simulation strategy has a strong impact on simulation performance.

metaSMT: A Unified Interface to SMT-LIB2
Heinz Riener, Mathias Soeken, Clemens Werther, Goerschwin Fey and Rolf Drechsler

A Comparison of Parallel SystemC Simulation Approaches at RTL
Bastian Haetzer and Martin Radetzki

 

11:00-11:30

Coffee Break

 

11:30-13:00

Requirements 

Chair: Peter Flake, Elda Technology Ltd
Co-Chair: Frank Oppenheimer, OFFIS 

Abstract:
This session considers various approaches to the formalization of requirements specifications. Natural language properties can be automatically translated into formal language properties in certain circumstances. The relationships between requirements can be formalized in graphical notation. The success of temporal property languages in the hardware domain inspires the application of similar ideas to the embedded software domain.

Automating the Translation of Assertions Using Natural Language Processing Techniques
Mathias Soeken, Christopher B Harris, Nabila Abdessaied, Ian G Harris and Rolf Drechsler

Semi-formal Representation of Requirements for Automotive Solutions using SysML
Liana Musat, Andi Buzo, Markus Hübl, Georg Pelz, Susanne Kandl and Peter Puschner

A Property Language for the Specification of Hardware-Dependent Embedded System Software
(Best Paper Candidate)
Binghao Bao, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel and Wolfgang Kunz

 

13:00-14:00

Lunch

 

14:00-15:30

Panel: Requirements for future AMS design support

Chairs: Joachim Haase, Fraunhofer IIS/EAS and Adam Morawiec, ECSI

Topics of the panel:
This panel intends to discuss the consequences of increasing complexity of electronic systems and their embedding into more and more complex and heterogeneous systems for the AMS design process from different points of view. The discussion will be centered around the following questions: What are the requirements from the industrial point of view? What can academia contribute to evolve and develop the basics of the underlying needed methods? What are the consequences for standardization processes and what are the expectations and opportunities of the EDA industry?
Finally, panellists and attendees will be invited to express their opinion on how the FDL can promote developments for future AMS design support.

Invited panellist:
Martin Barnasconi, NXP Semiconductors
Karsten Einwich, Fraunhofer IIS/EAS
Serge Garcia-Sabiro, Mentor Graphics
Christoph Grimm, TU Kaiserslautern
Giuseppe Scata, Texas Instruments

 
15:30-16:00

Coffee Break

 

16:00-17:30

Parallel Architectures

Chair: Alper Sen, Bogazici University
Co-Chair: Martin Radetzki, University Stuttgart

Abstract:
This session investigates different parallel architectures including GPUs, manycore SoCs, and manycore virtual platforms. Topics such as distributed simulation, task and communication migration as well as code synthesis are explored on these parallel architectures.

Distributed, loosely-synchronized SystemC/TLM simulations of many-processor platforms
(Best Paper Candidate)
Christian Sauer, Hans-Martin Bluethgen and Hans Peter Loeb

Dependable Task and Communication Migration in Tiled Manycore System-on-Chip
Stefan Wallentowitz, Volker Wenzel, Stefan Rösch, Thomas Wild, Andreas Herkersdorf and Jörg Henkel

Synthesizing Code for GPGPUs from Abstract Formal Models
Gabriel Hjort Blindell, Christian Menne and Ingo Sander

 

18:00-22:00

Social Event:  The Olympic Tower

The 2014 FDL Social Event invites you to visit the highest attraction of Munich – the Olympic Tower!

The magnificent tower of 291.28m will be visited just after the conference sessions finish. Keeping the right direction to the Olympiapark, we will start the journey from the Conference hotel by taking the underground. In a couple of minutes we will be right there.
 

More details at: http://www.ecsi.org/fdl/social-event

 

 

Thursday, October 16

 

09:00-10:00

Keynote 2:
 

Speaker: Bert Dexters and Dariusz Szymanski , Flanders' DRIVE

Abstract:
The presentation highlights the opportunities for an intensive use of behavioral and structural models during safety-related systems engineering. The key outcome of the research activities presented is the detailed mapping of the SysML model diagrams to specific steps of the safety engineering lifecycle. Innovative approaches for performing quantitative safety analysis based on the input of SysML models are also discussed. Finally, the positive influence of the new methodology on the effort consumption for safety-related engineering processes is elaborated. The presented study is based on an engineering methodology developed together with leading Flemish industrial partners for the design of safety-related E/E system according to international standards. The methodology can be applied not only for passenger cars but also in the agricultural, (earth moving) machinery and off-highway domains. This so-called Flanders’ ASIL methodology (FLAME) describes the processes, work products, roles and responsibilities and presents the links to the applicable requirements of the functional safety standards. The methodology is supported by a web based tool and can interact with other development tools. The synergies and gaps identified across the vehicle and machinery domains are also highlighted.

Bio:

Bert Dexters obtained his Masters degree in Electronics with the option ‘Information and Communication Technology’ in 2000 at the XIOS Hogeschool Limburg. He has profound knowledge and proven experience in the area of embedded systems and software development. He started his career as embedded software engineer at Philips for media streaming applications operating in both CMMI Level 2 and CMMI Level 3 certified organizations. After 4 years, he became senior Quality Assurance Officer and process improvement coordinator with expertise in CMMI (Levels 2 and 3) at Philips and NXP semiconductors. In this role, Bert led the connectivity group (multisite and multidisciplinary) within NXP Corporate Innovation and Technology towards CMMI Level 2. Since 2008, he took up the position of project manager for DisplayPort Tx Subsystem IP development. Complementary, he has experience as author of Quality and Safety Management Systems and is passionate coach in project and functional safety management, quality assurance and process improvement principles with a solid background as CMMI® appraiser and internal ISO 9001:2008 auditor. Today, Bert is account manager for Flanders’ DRIVE in the domains of Clean and Energy Efficient Vehicles and Intelligent Development Tools.

Dariusz Szymanski is Program Manager Intelligent Development Tools at Flanders’ DRIVE, Lommel. He received his Masters degree in Electrical Engineering in 1991 and his Ph.D. degree in Electrical Engineering in 2001 both from Silesian Technical University in Gliwice, Poland. He also did postgraduate courses in the fields of software engineering and project management. Since 1991 till 1995 he had been with Technical University in Gliwice where he specialized in the power system stability. He has been with Bombardier Transportation in Katowice, Poland since 1995 till 2007. He has got his professional experience in product development and product management in the field of railway interlocking systems and wayside equipment and also in the field of the industrial automation and automotive. In these domains he has gained experience in application of UML/SysML modeling in engineering practice and also in development and deployment of specialized SQL databases. Since 2007 till 2012 he was rector at the College of Mechatronics in Katowice. Since September 2012 he is with Flanders’ DRIVE. His interests includes functional safety, systems modeling.

10:00-10:30

 Coffee Break

 

10:30-12:30

Tutorial: Using UVM for Analog/Mixed-Signal Verification, A Practical Introduction

Presenters and authors: Eric Jeandeau and Tom Fitzpatrick, Mentor Graphics Corp.

Abstract:
This tutorial will provide an overview of The Universal Verification Methodology (UVM) verification environment and show how it facilitates the development of modular reusable verification components. It will describe the basics of test and environment creation, configuration and customization, and transaction-based stimulus generation and analysis, and show how these concepts can be extended to apply to an Analog/Mixed-Signal (AMS) design under test (DUT).

The tutorial will emphasize:

• How traditional techniques fall short

• How to assemble a UVM verification environment

• How to apply UVM concepts to generate analog stimulus from the environment

• How to apply UVM concepts to verification analysis to:

o extract analog measures in a UVM environment
o report on the behavior of the DUT
o feed DUT behavior back into the environment to adjust stimulus

• How to use the Unified Coverage Interoperability Standard (UCIS) to manage analog test results and measure functional coverage

• How automated test plan tracking works in an analog context

 

12:30-14:00

 Lunch

 

14:00-15:30

Natural Language Processing for Requirements Formalization

Chair: Mathias Soeken, University of Bremen

Abstract:
The special session presents works that show how natural language processing techniques can be exploited for requirements formalization. The session starts with an introduction to the fields of natural language processing and requirements formalization. Then three complementary talks follow that motivate and present techniques for quality measurement, requirements extraction, and requirements formalization. The first talk describes how natural language processing techniques can be used to assist the designer by automatically checking the quality of requirements. Requirements of high quality do not only avoid misunderstandings among designers but also enable a successful application of natural language processing techniques. The second talk presents theoretical work on a new text representation using graphs which is particularly suitable for identifying the most central and important parts of a text and hence can be helpful for requirements extraction. The third talk demonstrates how natural language requirements can automatically be translated into formal expressions. This is e.g. crucial for automatic verification and validation of specifications.

Quality Measures for Requirements based on Natural Language Processing
Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, and Rolf Drechsler

Weighted Dependency Graphs as a New Text Representation Model: General
Study

Marina Litvak, Natalia Vanetik and Mark Last

(Semi-)Automatic Translation of Legal Regulations to Formal Requirements: Expanding the Horizon of EDA Applications
Oliver Keszocze, Betina Keiner, Matthias Richter, Lucjan Suchy, and Robert Wille

 

15:30-16:00

 Coffee Break

 

16:00-17:30

Power

Chair: Christoph Grimm, TU Kaiserslautern
Co-Chair: Torsten Maehne, UPMC LIP6 

Abstract:
This session explores different aspects of power, which need to be modeled to enable a power-aware design of today's highly complex embedded systems. The first paper presents a new power-aware methodology for early specification, design-space exploration and verification of the designs’ power properties using so-called Power Contracts. The latter provide a formal link between the bottom-up power characterization of low-level system components and the top-down specification of the systems’ high-level power intent. The second paper presents a SystemC AMS extension to support modeling and simulation of externally as well as internally controlled electrical linear networks with ideal switches, which are a useful behavior abstraction technique to model semiconductor components in power system development. The last paper in this session describes a system-level multi-view modeling and co-simulation framework to deal with the high complexity of embedded systems, which is suitable to execute heterogeneous models for the thermal analysis of such systems.

Towards Satisfaction Checking of Power Contracts in Uppaal
Gregor Nitsche, Kim Gruettner and Wolfgang Nebel

SystemC-AMS Power Electronic Modeling with Ideal Instantaneous Switches
Leandro Gil and Martin Radetzki

Execution of Heterogeneous Models for Thermal Analysis with a Multiview Approach
Amani Khecharem, Carlos Gomez Cardenas, Julien Deantoni, Frédéric Mallet and Robert De Simone

 

17:30-17:45  Closing

 


FDL 2014 is organized with the techincal co-sponsorship of CEDA.
         

 

 

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