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FDL 2013
Forum on specification & Design Languages

September 24-26, 2013
Paris, France

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FDL 2013 Program
Click on the link in the table for the session description.

Tuesday, September 24

08:00-08:45 Registration & Welcome Coffee
08:45-09:00 Welcome to FDL
09:00-10:00 Keynote 1: Pieter J. Mosterman, MathWorks
10:00-10:30 Coffee Break
10:30-12:00 ISS: SystemVerilog MDE (1)
12:00-13:00 Lunch
13:00-14:00 Invited Speaker: Marleen Boonen, Methods2Business
14:00-15:30 ISS: Accellera Systems Initiative (1) MDE (2)
15:30-16:00 Coffee Break
16:00-17:30 ISS: Accellera Systems Initiative (2) Tutorial: Low Power
17:30-20:00 ESCUG Meeting


Wednesday, September 25

08:00-09:00 FDL TPC Meeting
09:00-10:00 Keynote 2: Twan Basten, TU Eindhoven
10:00-10:30 Coffee Break
10:30-12:00 DES (1)* Tutorial: Mentor (1)
12:00-13:00 Lunch
13:00-14:30 DES (2)* Tutorial: Mentor (2)
14:30-15:00 Coffee Break
15:00-16:30 DES (3) AFM/EAMS*
17:00-21:00 Social Event

* Sessions with best paper candidates

Thursday, September 26

08:00-09:00 FDL TPC Meeting (possibily continued)
09:00-10:00 Keynote 3: Quang-Huy Nguyen, Trusted Labs
10:00-10:30 Coffee Break
10:30-12:00 AFM ISS: Complex Heterogeneous Systems
12:00-13:00 Lunch
13:00-14:30 EAMS (1) Tutorial: UVM (1)
14:30-15:00 Coffee Break
15:00-16:30 EAMS (2) Tutorial: UVM (2)
16:30-16:45 Closing

Green column on left: Pasquier Amphithéâtre
Brown column on right: Salle des Thèse

Lunch: Salle Marie Curie
ESCUG Meeting: Pasquier Amphithéâtre
FDL TPC Meeting: Salle Marie Curie


Tuesday, September 24






Welcome to FDL

General Chair
Marie-Minerve Louërat, UPMC LIP6

General Co-Chair
Torsten Maehne, UPMC LIP6



Keynote 1: Pieter J. Mosterman, MathWorks

Engineered System Design and Integration—A Semantic Domain for Modeling Cyber-physical Systems

Chair:  Julio Medina, University of Cantabria
Co-Chair: Torsten Maehne, UPMC LIP6

The rapid ascent of computation as key driver in engineered system innovation has brought about the ability to implement features of unparalleled complexity. The set of behaviors that can be implemented on a modern digital processor transcends by orders of magnitude what can be implemented in analog hardware of a comparable form factor. Moreover, the flexibility of computation combined with its ability to interface with most any other computational feature has made it the preferred (if not ideal) system integration technology. All of these benefits are accompanied by distinct challenges, though. Specifically, the computational elements that are dispersed throughout a system have come to broadly interact with one another either directly or across physical elements. This interaction has given rise to a range of system integration issues that are difficult to tackle systematically. Moreover, networking technology has been the catalyst for a class of systems of systems with interaction modalities that comprise both the physical world as well as cyberspace. Features of such cyber-physical systems consist of functionality that is implemented in various separately produced systems. This shared functionality across independent systems in their own right further complicates related integration issues. The presentation discusses principles of engineered system design and highlights some integration issues. Further, cyber-physical systems are conceptualized along with a spectrum of modeling formalisms employed to design such systems. Finally, a stream-based functional semantic domain to support the corresponding multi paradigm modeling approaches is presented.

Full bio at:
Pieter J. Mosterman is a Senior Research Scientist at MathWorks in Natick, MA working on design automation technologies. He also holds an Adjunct Professor position at the School of Computer Science of McGill University. Before, he was a Research Associate at the German Aerospace Center (DLR) in Oberpfaffenhofen. His Ph.D. is in Electrical and Computer Engineering (Vanderbilt University, Nashville, TN) and his M.Sc. in Electrical Engineering (University of Twente, Netherlands).

Dr. Mosterman designed the Electronics Laboratory Simulator that was nominated for The Computerworld Smithsonian Award by Microsoft Corporation in 1994. In 2003, he was awarded the IMechE Donald Julius Groen Prize for his paper on the modeling and simulation environment HyBrSim. Dr. Mosterman has been Editor-in-Chief of SIMULATION: Transactions of SCS and Guest Editor for IEEE Transactions on Control Systems Technology, and ACM Transactions on Modeling and Computer Simulation. He has chaired over 30 scientific events, served on over 100 International Program Committees, published over 100 peer reviewed papers, and is inventor on over 40 awarded patents



Coffee Break


MDE 1: Modeling Languages Extensions and Best Practices

Chair: Julio Medina, University of Cantabria
Co-Chair: Gjalt De Jong, ArchWorks

Model-based software development is called to be one of the most promising software engineering approaches. This session explores the use of standard modelling languages in this aim. Our first paper presents the use of MARTE and its real-time modes specification for the development of cross-layer self-adaptive real-time embedded systems. The second explores its use over an autonomous robot use case for the application of MAST schedulability analysis tools for model-based performance analysis. Finally, the difficult task of design space exploration for the allocation of UML composite structures in the modelling of distributed systems is explored.

Fine-grain Adaptation for Real Time Embedded Systems using UML/MARTE Profile

Mouna Ben Said, Yessine Hadj Kacem, Nader Ben Amor (University of Sfax, ENIS, CES Laboratory), and Mickaël Kerboeuf (University of Brest)

Performance Analysis Method for RT Systems: ProMARTES for Autonomous Robot
Konstantinos Triantafyllidis, Egor Bondarev, and Peter H. De With (Technische Universiteit Eindhoven)

Split of Composite Components for Distributed Applications
Ansgar Radermacher, Arnaud Cuccuru, Sebastien Gerard (CEA-LIST), and Brahim Hamid (University of Toulouse)



SystemVerilog: the New Standard 

Chair: Kaiming Ho, Fraunhofer

The SystemVerilog language is fast becoming the dominant language used in the design and verification of digital systems.  From its roots in the Verilog language, the latest revision (IEEE 1800-2012) has grown into a multi-faceted language that solves problems previously requiring the combination of multiple languages.  Each of the speakers in this session has been closely involved with, and contributed to, the development of SystemVerilog.  They will share their views, from a user’s and from an implementer's perspective on the current status and future direction of the language. The session will serve to introduce new and current users to the capabilities of the language, enticing them to adopt it for their next project.  At the same time, research groups are encouraged to participate in developing SystemVerilog methodologies and tools, and suggest new directions for language improvement. 

Why SystemVerilog?
Peter Flake (Elda Technology Ltd)

The Unique Challenges of Debugging Design and Verification Code Jointly in SystemVerilog
Dave Rich (Mentor Graphics)

If SystemVerilog Is So Good, Why Do We Need the UVM?
Jonathan Bromley (Verilab)






Invited Speaker: Marleen Boonen, Methods2Business

State-of-the art Embedded System Design

Chair: Gjalt De Jong, ArchWorks

The invited talk will focus on the key technology trends in Electronic (EDA) and Software Design Automation (SDA) that have moved the design of hardware and software to higher levels of abstractions, which could effectively be realized thanks to supported standards such as SystemC/TLM, SystemVerilog, AMS, UVM, and IP-XACT.

The early availability of a high performance virtual prototype is no longer point of discussion to reduce software development costs while speeding up development time and increasing product quality. The availability of industrial tools based upon the SystemC/TLM2 and IP-XACT standards have made it possible to highly automate the creation of high speed platforms suitable for bringing-up real software applications while offering fully synchronized and unified hardware/software debugging.

The ROI for SystemC/TLM2 can be even further increased by making SystemC transaction-level models the design entry point for high level synthesis which should lead to more scalable, more flexible, and more cost effective IP development while optimizing verification efforts by including the models in the virtual platforms.
The talk will furthermore address the theme of the 50th Design Automation conference this year in Austin, which was about the need for Software-Driven EDA in order to deal with the more prominent roles of software in current embedded systems. The audience will be introduced to a unique Model Driven Software Design approach generating defect-free software from mathematically proven models, which in combination with traditional assertion-based verification in SVA or PSL is leading towards formally proven embedded system design.

The speaker will found her statements with success stories from the industry.


Marleen Boonen, CEO, founded Methods2Business end 2010 with the ambition to develop & deploy design methods for making hardware and software IP development scalable, flexible, and first time right in less time.

To achieve her goal, she established strategic partnerships with leading technology providers in Electronic (EDA) and Software Design Automation (SDA).

Today, Methods2Business takes advantage of high end system level design solutions and formal verification methods in customer engagements and is a regular presenter at international conferences.  The company received the Cadence best paper award for System Level Design at CDNLive EMEA 2012.

Marleen brings to her role of CEO a broad expertise in R&D and management having served for 25 years at Philips and NXP. From 2000 onwards, she was heading an innovation team responsible for building the company-wide System Level Design Flow. With her team, she actively contributed to the standardization of SystemC/TLM and IP-XACT and was a MT member of the European project “SPRINT”, the Open SoC Design Platform for Reuse and Integration of IPs.

Marleen earned in 1985 the diploma of Burg. Ir. (equivalent to a master’s degree) in Electronic Engineering from the Catholic University Leuven (KU.Leuven), Belgium.



MDE 2: Model Driven Engineering at Work

Chair: Gjalt De Jong, Archworks
Co-Chair: Julio Medina, University of Cantabria

This session presents three interesting efforts. The first proposes the mapping of activity diagrams into Bluespec System Verilog. It suggests a rule based transformation from activity diagrams to the PRISM formalism and to the Bluespec language. The second presents an energy consumption optimization tool for designers dealing with wireless sensor nodes, modeling energy consumption in wireless sensor nodes from SystemC models. The third presents an MDD approach for developing smartphone apps independently of a specific platform.

A Formal Verification Framework for BlueSpec System Verilog
Samir Ouchani, Otmane Aït Mohamed, and Mourad Debbabi (Concordia University)

A Function Approach for Simple Wireless Sensor Node Energy Consumption Modeling
Aina Andriamampianina Randrianarisaina, Olivier Pasquier and Pascal Chargé (IETR, University of Nantes)

Model-Driven Design for the Development of Multi-Platform Smartphone Applications
Giulio Botturi, Emad Samuel Malki Ebeid, Franco Fummi, and Davide Quaglia, (University of Verona)



Accellera Systems Initiative – The Value of EDA and IP Standards for Design and Verification

Chair: Martin Barnasconi, NXP Semiconductors

System, software, and semiconductor design are converging to meet the increasing challenges to create complex integrated circuits and system on chips. This convergence has brought to the forefront the need for a single organization to facilitate the creation of system-level, semiconductor design, and verification standards. The Accellera Systems Initiative, which was formed in 2011 after the merger of Accellera and the Open SystemC Initiative (OSCI), addresses the needs of the system and semiconductor designers who must find new and smarter ways to design, verify, and produce increasingly complex chips.

In this industrial session, the Accellera Systems Initiative will give a technical update regarding some of the latest advancements of EDA and IP standardization, and will present the benefits and value of its standards for the design and verification of integrated circuits and systems. The session will highlight the following standards:

  • IP-XACT – Technical update on the developments of the standardized extensions for power, analog/mixed-signal and physical design planning. In addition, bus definitions are defined for commonly used interfaces.
  • SystemC AMS 2.0 – Introduction of the recently announced SystemC AMS 2.0 standard, which offers more dynamic and reactive behavior to develop mixed-signal virtual prototypes.
  • Universal Verification Methodology (UVM) 1.1 The UVM standard is the recognized industry standard to create modular, scalable and reusable verification environments. The features of the UVM standard and its reference implementation are explained.

In addition, an overview is given on the other standards of the Accellera Systems Initiative, as well as its contributions to the recently announced IEEE standard updates such as IEEE1800 (SystemVerilog) and the GetIEEE program.


  • Laurent Maillet Contoz, STMicroelectronics, Presenter for IP-XACT
  • Martin Barnasconi, NXP Semiconductors (session chair), Presenter for SystemC AMS 2.0
  • Dennis Brophy, Mentor Graphics, Presenter UVM
  • Yatin Trivedi, Synopsys, Presenter other standards and IEEE program



Coffee Break



Accellera Systems Initiative – The Value of EDA and IP Standards for Design and Verification (continued)



Tutorial: Design of Energy-Aware Embedded Systems

Organizers & Speakers:
Christoph Grimm, TU Kaiserslautern
Tom Kazmierski, University of Southampton
Jan Haase, TU Vienna

Embedded systems have become more and more mobile, and in some applications, even energy autonomous operation is required. The design of such systems is a challenge, as power and energy consumption is not defined on a single layer (e.g., technology). Instead, all layers from technology up to application are contributing to power consumption. The tutorial gives an overview of approaches to reduce power consumption from technology, circuit design up to MAC, operating, and application layers. As an approach to establish X-layer energy awareness, SystemC-based power profiling is introduced.



The European SystemC Users' Group (ESCUG) announces its 28th meeting at FDL Conference 2013 in Paris on Tuesday, September 24th, 2013, 17:30 h (closing 20:00 h). This meeting will give the users community and Accellera a platform to discuss their experience with new design and verification technologies.

The meeting will be free of charge!

Room: Pasquier Amphitheatre

17:30 h

Opening and Welcome
Christoph Grimm, TU Kaiserslautern, DE

17:35 h

Accellera General Update
Dennis Brophy, Accellera Systems Initiative, US

17:50 h

Multi-language Working Group Update
Martin Barnasconi, Accellera Systems Initiative, NL

Language Working Group Update
Philipp A. Hartmann, OFFIS, DE

18.20 h

VERDI Project Work: UVM-SystemC
Martin Barnasconi, NXP, NL

18:50 h

Modelling, simulation, and advanced tracing for extra-functional properties in SystemC/TLM
Philipp A. Hartmann, OFFIS, DE

19:20 h

A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS
Ramy Iskander, UPMC, Department SOC, FR

19:50 h

Wrap-Up and Closing
Christoph Grimm, TU Kaiserslautern, DE

We're looking forward to meeting you in Paris!



Wednesday, September 25


FDL TPC Meeting



Keynote 2: Twan Basten, Eindhoven University of Technology and TNO-ESI

Making Data Flow, Dynamically

Chair: Martin Radetzki, University Stuttgart

Many of today's embedded systems are data-intensive. They are moreover more and more often operating in an open, dynamic environment with varying processing workloads and changing resource availability. Dataflow models of computation are well-suited for the model-driven design of data-intensive embedded systems. Traditional dataflow models like synchronous dataflow cannot efficiently cope with the dynamics of modern systems. Novel computational models such as scenario-aware dataflow have been developed to address this challenge. In this presentation, I will present an overview of model-driven embedded-system design using dataflow models, surveying the state of the art in system synthesis and highlighting some remaining challenges.

Twan Basten is a professor of computational models at the Eindhoven University of Technology (TU/e) and a senior research fellow of TNO-ESI, Embedded Systems Innovation by TNO. Both TU/e and TNO-ESI are located in Eindhoven, the Netherlands. Twan Basten chairs the Electronic Systems group at TU/e. His research interest is the design of resource-constrained embedded and cyber-physical systems, focusing on computational modeling and design automation. Twan Basten served in over 50 TPCs. He (co)authored 1 book and over 150 scientific publications, of which four received a best paper award. He (co)supervised 11 PhD degrees. Twan Basten is a senior member of the IEEE and a life member of the ACM. Contact him at



Coffee Break



DES 1: SystemC Infrastructure and Extensions 

Chair: Peter Flake, Elda Technology Ltd
Co-Chair: Frank Oppenheimer, OFFIS 

Through proposed extensions of the core library and new methodology-specific libraries, SystemC is continuously being improved in order to achieve better modeling capabilities and to meet user needs. The first paper in this session proposes the concept of combining SystemC events with TLM transactions so as to simplify and systematize synchronization in TLM models. The second paper introduces a framework that enables static analysis of SystemC models. The third paper presents a new version of a library for logging and tracing that goes far beyond SystemC's built-in tracing mechanism.

SystemC Transaction Level Modeling with Transaction Events
(Best Paper Award)
Bastian Haetzer and Martin Radetzki (University Stuttgart)

SystemC-Clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models
Anirudh Kaushik and Hiren D. Patel (University of Waterloo)

Advanced Features for Industry-Level Logging and Tracing of C-based Designs
Wei Hong, Jyoti Joshi, and Alexander Viehl (FZI-Forschungszentrum Informatik Karlsruhe), Nico Bannow, Angela Kramer, and Hendrik Post (Robert Bosch GmbH), Oliver Bringmann and Wolfgang Rosenstiel (University of Tuebingen)



Tutorial: From Application Requirement to IP Requirement

Organizer: Marius Sida, Mentor Graphics
Chair: Marie-Minerve Louërat, UPMC LIP6
Juergen Schaefer, Infineon
Michael Bierl, Mentor Graphics
Marius Sida, Mentor Graphics

In the automotive industry a complex SOC like a high-end microcontroller is used in more than different 100 applications. These requirements are the needed base to define the safety goals including the related diagnostic coverage and the latent fault coverage. This process forces the tracing of system- and application requirements and the related use cases.

The ISO26262 standard introduces a V-model related development process which is mandatory for above-mentioned systems.

This tutorial will cover the functional safety subject, from various angles, like system developer (SV) and electronic design automation (EDA) capabilities.

From functional safety point of view, the supply, reset, and clock concepts are the most critical parts of the SOC architectural selection process.

The value chain in the automotive industry is partitioned into OEM, system supplier (Tier1), and semiconductor supplier. Typically, the definition process of the ECU- and the SOC architecture works concurrently. To verify continuously the SOC architecture against the fluctuating set of system requirements, an extendible meta-model of the SOC architecture must be available. The meta-model itself is a high-level architectural exploration with the objective to take the right decision during the SOC concept phase, which means the model does not contain any implementation details. In addition, this kind of model supports the formal safety assessments (FMEDA) required by ISO26262 in a very early project phase.

While the importance of ISO26262-based design and verification processes are increasing within the automotive industry, in the area of SoC design, system architects need to be able to make viable architecture decisions early in the design cycle, by analyzing, debugging, and prototyping complex systems before the RTL stage. In this tutorial, we will present you a SystemC-TLM-2.0-based technology, which allows hardware and software engineers to develop and verify their product within a predictable and productive design process that leads to first-pass success.

Last but not least, analog and mixed-signal modules are integral part of almost all automotive integrated systems. Metric-driven verification approach has been in use for digital design verification and adopting it for analog design can bridge the verification methodology gap between verification of analog and digital designs. In this tutorial, we will present ideas and possibilities around metric driven verification for Analog and Mixed-Signal design. We will use examples like an operational amplifier - used in a LDO circuit and other - including the link to the test plan and the requirement tracking system.






DES 2: Platform-based Design

Chair: Jean-Philippe Babau, LISYC, UBO
Co-Chair: Martin Radetzki, University Stuttgart

This session features three new approaches that support platform-based design. The first paper shows how predictable platforms can be characterized to form a basis for virtual prototyping of real time systems. The second paper supports software allocation in networked automotive system platforms. The third paper presents a formal approach that enables the representation of the mapping and scheduling of tasks onto embedded platforms.

Rapid Virtual Prototyping of Real-Time Systems using Predictable Platform Characterizations
(Best Paper Candidate)
Seyed Hosein Attarzadeh Niaki, Marcus Mikulca, and Ingo Sander (Sweden Royal Institute of Technology - KTH)

Graph-based Approach for Software Allocation in Automotive Networked Embedded Systems: A Partition-and-Map Algorithm
Yasser Shoukry (Ain Shams University), Ajay Kumar, M. Watheq El-Kharashi, Ghada Bahig (Mentor Graphics), and Sherif Hammad (Ain Shams University)

Representing Mapping and Scheduling Decisions within Dataflow Graphs
Christian Zebelein and Christian Haubelt (University of Rostock), Joachim Falk, Tobias Schwarzer, and Jürgen Teich (University of Erlangen-Nuremberg)



Tutorial: From Application Requirement to IP Requirement (continued)



Coffee Break



DES 3: Simulation, Analysis and Validation 

Chair: Frank Oppenheimer, OFFIS 
Co-Chair: Martin Radetzki, University Stuttgart 

Efficient simulation, static analysis, and model transformation are key techniques to enable design validation and design space exploration. The first paper shows a method for switching between models of different abstraction levels and its application to trade off speed and accuracy in network-on-chip simulation. The second paper combines simulation with analytical techniques to provide estimates that guide the design space exploration of real time systems. The third paper introduces model transformations and validation methods that open an automated path from algorithm design to ESL design.

Fine Grained Adaptive Simulation with Application to NoCs
Marcus Eggenberger and Martin Radetzki (University of Stuttgart)

Combining Analytical and Simulation-based Design Space Exploration for Time-Critical Systems
Fernando Herrera and Ingo Sander (Sweden Royal Institute of Technology - KTH)

Bridging Algorithm and ESL Design: Matlab/Simulink Model Transformation and Validation
Liyuan Zhang, Michael Glass, Jürgen Teich, and Nils Ballmann (University of Erlangen-Nuremberg)



AFM/EAMS: Verification of Heterogeneous Systems: Theory and Industrial Experiences 

Chair: Christoph Grimm, TU Kaiserslautern 
Co-Chair: Emmanuelle Encrenaz, UPMC LIP6 

The verification of heterogeneous systems, in particular of analog/mixed-signal system, is still a problem. In this session the first two research papers describe new methods to verify analog/mixed-signal systems using an assertion-based approach.  The last two papers give an insight into industrial practice. 

A New Assertion Property Language for Analog/Mixed-Signal Circuits
(Best Paper Candidate)
Dhanashree Kulkarni, Andrew Fisher, and Chris Myers (University of Utah)

Integrating Circuit Analyses for Assertion-based Verification of Programmable AMS Circuits
Dogan Ulus, Alper Sen, and Faik Baskaya (Bogazici University)

How to survive the Verification of the latest generation of Automotive System On Chip
(short presentation)
Arnaud Laroche and Jerome Kirscher (Infineon)

A Novel Approach for Assertion Based Verification of DDR Memory Protocols
(short presentation)
Moustafa Kassem, Mohamed Abdelsalam, Marianne Michel, and Ashraf Salem (Mentor Graphics)



Social Event

The 2013 FDL Social Event will start with a boat cruise on the infamous Seine River and will conclude with dinner on the picturesque île Saint Louis.

We will leave at 17:00 from the conference venue to the port. It is a lovely 30 minute walk or a 20 minute metro ride. If you prefer to take the metro, please ask for a ticket at the registration desk.

Following the boat ride, we will take a 15 minute walk to the restaurant. Please let us know at registration if you have a disability and we will arrange a taxi.

By Metro, take the M4 at Odéon towards Porte de Clignancourt. Got off the M4 at Châtelet to make transfer. At Châtelet, take the M1 toward Château de Vincennes and get off at Bastille.

Canauxrama Cruise, Port de l’Arsenal, facing n°50 bd de la bastille 75012 Paris
Restaurant Nos Ancêtres les Gaulois, 39 Rue île Saint Louis en île, 75004 Paris

Full details at:



Thursday, September 26


FDL TPC Meeting (possibily continued)



Keynote 3: Quang-Huy Nguyen, Trusted Labs

Formal Verification for Certifying Security IC in EAL7 Level

Chair: Dominique Borrione, TIMA
Emmanuelle Encrenaz, UPMC LIP6

Security IC provides the hardware platform of the tamper-resistant embedded devices such as smart cards and wireless sensor nodes. These devices are built to operate in a hostile environment with limited computing resources. For efficiency reason, their security functions should be fairly shared between the hardware platform and the embedded software.

Being created to increase the trust and confidence in the IT products, the Common Criteria (ISO/IEC 15408) defines the security requirements on the whole product life-cycle (from specification to deployment). In particular, the high-level certifications (i.e., EAL6/7) require a formal proof of the correctness and also strong evidence of the robustness (of the implemented security functions).

In this talk, we describe the use of formal verification in the top-level security certification of the security IC. We focus on the security aspect of the circuits rather than their functional behaviour.

Quang-Huy Nguyen is a Formal Methods expert and senior security consultant in Trusted Labs since 2011. Before, he spent nearly 10 years in the R&D activities of Gemalto, the world-leading provider of smart cards and related solutions. He successfully led several high-level certification projects including the two world-first EAL7 certifications of a smart card IC and of a smart card OS. Being a Certified Information Systems Security Professional, Quang-Huy Nguyen also holds a Ph.D. in Computer Science. His research activity focuses on securing embedded devices by formal methods.



 Coffee Break



AFM: Application of Formal Methods for Design Space Exploration and Refinement 

Chair: Dominique Borrione, TIMA Laboratory 
Co-Chair: Ashraf Salem, Ain Shams University

The first paper tackles energy-efficient component selection and proposes a heuristic algorithm to solve this NP-hard problem. The second paper presents a refinement-based design approach for Systems-on-Chip, supported by model checking technology. The last contribution introduces a technique based on constraint solving for power estimation.

Optimal Component Selection for Energy-Efficient Systems
Matthias Sauppe, Thomas Horn, Erik Markert, and Ulrich Heinkel (TU Chemnitz), Hans-Werner Sahm and Klaus-Holger Otto (Alcatel-Lucent AG, Nuremberg)

Assisting Refinement in System-on-Chip Design
Mokrani Hocine, Ameur-Boulifa Rabéa (Telecom-ParisTech), and Emmanuelle Encrenaz (LIP6 / University Pierre et Marie Curie & CNRS)

Design Space Exploration for Cyber Physical System Design using Constraint Solving
Benny Höckner, Petra Hofstedt, Sascha Kaltschmidt, Peter Sauer (Brandenburg University of Technology Cottbus), and Thilo Voertler (Fraunhofer IIS/EAS)



Verification and Prototype Validation of Complex Heterogeneous Systems

Chair: Karsten Einwich, Fraunhofer

When designing and building a complex system the checking of its correctness is a challenge. The focus of this special session will be on the methodologies and tools for verification and validation (lab based prototype testing) of heterogeneous or mixed-signal systems with the objective to provide an overview of the best current practices in the field. This special session is organized by the participants of the European FP7 project Verdi (Verification for heterogeneous Reliable Design and Integration) <>, which focusses on the system-level verification and validation using SystemC and its AMS extensions.

FPGA-based SoC Emulator for HW/SW Functional Verification of Sophisticated Automotive Safety Critical System
Thang Nguyen, Infineon Austria

Virtual Platform for Automotive Electronic Systems Development
Ingmar Neumann, Continental TEVES AG & CO. oHG

UVM Test-bench Generation Flow
Ronan Lucas, Magillem Design Services

System Level Verification/Validation for heterogeneous Systems
Thilo Vörtler, Fraunhofer IIS/EAS






EAMS 1: Modeling Communication and Circuit’s Behavior 

Chair: Tom Kazmierski, University of Southampton
Co-Chair: Torsten Maehne, UPMC LIP6  

This session addresses difficult challenges in analog and mixed-signal modeling and simulation. The first paper proposes a model to describe the nonlinear behavior of a memresistor as a hybrid system and presents its implementation in VHDL-AMS. The second paper gives an overview of AMS circuit event-driven (real number) modeling, proposes a higher level of abstraction for this kind of modeling and describes experiences of implementing the proposed technique in various HDLs.  The final paper addresses the high-speed communication between digital systems, which exhibits analog behaviour. Analog models are needed to evaluate correctly the impact of communication links on signal integrity. The paper discusses how this can be done at a high level of abstraction in SystemC-AMS.

Hybrid Dynamical Systems for Memristor Modelling
Joachim Haase and André Lange (Fraunhofer IIS/EAS)

Event-Driven (RN) Modeling for AMS Circuits
Serge Garcia Sabiro (Mentor Graphics)

Modeling of Signal Integrity in Bus Communications with Timed Data Flow SystemC-AMS
Ruomin Wang, Julien Denoulet, Sylvain Feruglio, Farouk Vallette, and Patrick Garda (LIP6 - UPMC)



Getting Started with UVM

Organizer: John Aynsley, Doulos
Presenter: Guillaume Joli, A.L.S.E., France

This tutorial will give a practical introduction to using UVM, the Universal Verification Methodology for SystemVerilog. UVM is an Accellera standard SystemVerilog class library that enables verification code reuse and encourages best practice when building constrained random verification environments. This session will take a very practical approach to UVM, teaching some of the most common and important features of UVM by presenting a series of fully detailed code examples. This session is aimed at hands-on engineers, who want to start writing UVM code themselves and are looking for some specific advice on the best place to start, the right UVM features and coding idiom to use, and the pitfalls to avoid. A basic understanding of object-oriented programming is assumed.


  • An introduction to class-based verification environments in SystemVerilog
  • A summary of the SystemVerilog features used for class-based verification
  • The principles and goals of UVM
  • A first UVM example
  • Interfacing between the class-based verification environment and the design-under-test
  • Communication between the UVM sequencer and driver
  • Nested sequences and the configuration database
  • Sequence callbacks and factory overrides
  • The standard reporting mechanism
  • Communication using analysis ports and exports
  • The UVM register layer



 Coffee Break



EAMS 2: Model Generation for Embedded Analog/Mixed-Signal Systems 

Chair: Jan Haase, TU Vienna
Co-Chair: Francois Pecheux, UPMC LIP6 

In the first presentation the authors introduce a new approach for simulating multi-domain systems modeled in SysML by focusing on the definition of concrete semantics for SysML to enable correct interpretation of heterogeneous models.  The next presentation shows a way to generate homogeneous (SystemC AMS or C++) code for heterogeneous systems by using a formal representation as an intermediate representation.  The presentation concluding this sesssion presents the concept structure model to express the design feature variety in analog circuits.

Multi-Paradigm Semantics for Simulating SysML Models using SystemC-AMS
Daniel Chaves Café (Supelec), Filipe Vinci Dos Santos (Thales), Cécile Hardebolle, Christophe Jacquet, and Frédéric Boulanger(Supelec)

Code Generation Alternatives to Reduce Heterogeneous Embedded Systems to Homogeneity
(short presentation)
Franco Fummi, Michele Lora, Francesco Stefanni, and Sara Vinco (University of Verona)

Modeling the Analog Circuit Design Feature Variety
Cristian Ferent and Alex Doboli (State University of New York at Stony Brook)



Getting Started with UVM (continued)


16:30-16:45  Closing


FDL 2013 is organized with the techincal co-sponsorship of CEDA.



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