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FDL 2011
Forum on specification & Design Languages

September 13-15, 2011
Oldenburg, Germany


European SystemC User's Group Meeting

We are pleased to announce the 24. European SystemC User's Group Meeting, which will take place co-located with FDL'11 in Oldenburg/Germany on

Tuesday, September 13th, 2011

Please mark September 13th, 2011 for our next European SystemC User's Group Meeting in your calendar. Detailed information and the invitation will be sent by email and will also be available on our web site:

We will traditionally provide possibilities for SystemC users to present and discuss their experience with SystemC. Participants who are interested in presenting their work are very welcome and should send title and a short abstract until August 19th, 2011 to axel [dot] braun [at] informatik [dot] uni-tuebingen [dot] de.

We are also providing a Suppliers Forum at this meeting. This part of the meeting is a platform for SystemC EDA vendors to present technical views of theirs methodologies, tools, and libraries (please do not submit any sales oriented presentation). If you are interested, please send a description of
the demonstration until August 19th, 2011 to axel [dot] braun [at] informatik [dot] uni-tuebingen [dot] de.

We are looking forward to your submissions!
Axel Braun, Wolfgang Rosenstiel

The 24. European SystemC Users Group Meeting is supported by the
Open SystemC Initiative and these Global Sponsors:

ARM, Cadence, CoWare, Doulos, Forte, Synopsys,
Mentor Graphics, Virtutech, Extreme EDA

FDL Planning Committee Meeting

The FDL PC Meeting will take place Thursday, September 15 during lunch from 12:30-14:00.
Please click here to view a full list of committee members.

Tutorial: High Level Synthesis: from C++ to VHDL – part 1

Tuesday, September 13
By CoSynth (, Oldenburg, Germany
• System-On-Chip modeling in C++ and SystemC
• Refinement from functional specification to synthesizable RT-like description
• Using the CoSynth synthesis tool to generate VHDL from SystemC
• Optimization strategies and optimal partitioning of the system
• (Optional) Getting the design down to the FPGA
Testing environment for HLS workflow

ABD Panel: Assertions Propagation, Refinement and Reuse across Abstraction Levels and Description Languages

Tuesday, September 13
Chair: Harry Foster, Mentor Graphics
Members: To be confirmed

Tutorial: Parallelize your TLM Simulation of MPSoC on SMP Workstations!

Wednesday, September 14
Rauf Salimi Khaligh, University of Stuttgart
Bastian Haetzer, University of Stuttgart
François Pêcheux, Université Pierre et Marie Curie, LIP6 Laboratory
Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine still uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of an architecture containing hundreds of processor cores, and involving hundreds of SC_THREADs to be scheduled. In this tutorial, we present a review of current research activities towards parallel TLM simulation. We show how a synchronous PDES (Parallel Discrete Event Simulation) scheme can be employed in conjunction with the TLM feature of temporal decoupling to achieve speedup through parallel execution of multiple discrete event simulation kernels. An alternative approach is based on the asynchronous PDES principle, which will be introduced. This allows us to derive TLM simulation tricks such as temporal decoupling and result oriented modeling instead of postulating them as in current standards. We then describe a PDES based general component modeling strategy for shared memory MP2SoCs and associated tools for the parallel TLM simulation of these manycore architectures. The proposed SMP version of the SystemC kernel (named SystemC-SMP) can run advantageously on multicore workstations. As the speedup obtained by parallel simulation heavily depends on the communication pattern between the parallel tasks, the influence of various locality characteristics for the software application running on the simulated MPSoC is also detailed.

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