Keynotes

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Keynote 1:
IoT Trends and Innovative Applications

Speaker: Roberto Zafalon, STMicroelectronics, Italy

Abstract:
The keynote will tackle with the three major IoT challenges today: interoperability, security, and business model (monetization). The strong enabling technologies roots (i.e. semiconductor and IP Design) will set the stage for a comprehensive view of the key IoT end-markets and of the most innovative applications expected to boost the massive deployment of IoT by the next 4 years.

 
CV:
Dr. Roberto Zafalon is EU Technology Programmes Director - STMicroelectronics, Agrate Brianza (Milano), Italy, in charge to foster and leverage the link between ST technology groups and the R&D cooperative EU programs. In his current capacity since July 2007, he elaborates the vision and roadmap, seeks for project financing and drives industrial R&D teams to pursue innovative solutions in the field of IoT, embedded systems and nanolectronics, for corporate product divisions and labs. He is Steering Board member of ARTEMIS-IA and EPOSS and, as such, he is member of the ECSEL Governing Board.
He currently is, and has been in the past, General Project Manager and Coordinator of major Projects under FP6, FP7, ENIAC and ECSEL, including Large scale KET Pilot Lines. He has been selected by FP7-ICT, ARTEMIS JU, ECSEL and H2020 LEIT as independent expert to review the project submitted to some past calls.
From 2000 until June 2007, he has been the head of the Competence Center for Low Power System Design at the Advanced System Technology, the ST’s Corporate System R&D group. The main targets have been the next generation's embedded systems trade-offs, including algorithmic and architectural design exploration and power optimization, SW/HW partitioning and RF optimization and co-verification, power profiling, estimation and macro-modeling, energy efficient Network on Chip and RT-OS featuring dynamic power management policies.
As far as the on-chip communication is concerned, shared bus interconnects represent only a partial, short-term solution, because of their limited scalability. We focus on parallel and scalable interconnect architectures to support the rapidly growing communication bandwidth’s requirement, both in terms of Low Power Multi Processor Platforms and Energy Efficient NoC’s.
 
  

Keynote 2:
Programming in a Heterogeneous World

 

Speaker: Jan Kuper, QBayLogic, The Netherlands
 

Abstract:
Around 2005 the fast growth of the single core CPU was more or less over, after which both in industry and in academia a lot of effort was put into the development of alternative computing platforms, such as multi and many core archtectures, systems-on-chip, FPGAs and more course grain reconfigurable archtitectures, etcetera. However, programming many of these new platforms became a serious issue, and many attempts are undertaken to define translation mechansims from the well known and well developed programming methodology into often low-level platform specifc programming languages. As an example we just mention the existence of several high level synthesis tools for the specification of an FPGA, which translate among others C, C++, Java into VHDL or Verilog. However, none of these tools works really pleasantly.
In this talk we will argue that that the above described approach is doomed to fail because the way each type of computing platform deals with its internal space and time in a different way. Instead, we will argue that we should start from a really platform independent level, for which mathematics is a good candidate. It must be possible to develop compilers that translate - a subset of - mathematics into platform specifc languages. As an example will show the compiler CλaSH, which translates a close to mathematics specification into VHDL or Verilog for FPGA specification.

 

CV:
Jan Kuper studied logic and mathematics at the University of Twente, where he got his Master degree (with honours) in 1985. In 1994 he received his PhD degree under the supervision of Henk Barendregt on the foundations of mathematics and computer science. He developed a theory of partial functions and generalized to a theory of binary relations, which both are strong enough to be a foundation of mathematics.

He worked as a lecturer at the University of Leiden, as a researcher at the University of Nijmegen, and he now is an assistant professor at the university of Twente. His main fields of interest are philosophical and  mathematical logic, functional programming and hardware specification from a mathematical perspective. Based on the functional programming language Haskell he initiated the design of a mathematical language as a specification language for computer architectures (called CλaSH). Recently he co-founded QBayLogic, a company that designs FPGAs using CλaSH.

He published on the foundations of mathematics, lambda calculus, mathematical logic, specification languages for computer architectures, and on concrete FPGA designs.

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