FDL 2017 Advance Program

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Session 1: Modelling and Simulation

 
1.1 Fault Analysis in Linear Analog Circuits through Language Manipulation and Abstraction
    Enrico Fraccaroli, University of Verona
    Franco Fummi, University of Verona
    Francesco Stefanni, EDALab
    Mark Zwolinski, University of Southampton
 
1.2 Actor Fission Transformations for Executing Dataflow Programs on Manycores
    Essayas Gebrewahid, Halmstad University
    Zain Ul-Abdin, Halmstad University
 
1.3 Rethinking of I/O-Automata Composition
    Sarah Chabane, University M’Hamed Bougara
    Rabea Ameur-Boulifa, Université Paris-Saclay
    Mohamed Mezghiche, University M’Hamed Bougara
 
 

 
Session 2: Languages and Design Methods for Time-critical Systems

S2.1 Real-Time Ticks for Synchronous Programming
    Reinhard von Hanxleden, Christian-Albrechts-Universität zu Kiel
    Timothy Bourke, INRIA, PARKAS Team
    Alain Girault, INRIA, SPADES Team

S2.2 Symbolic Simulation of Dataflow Synchronous Programs with Timers
    Guillaume Baudart, ENS
    Timothy Bourke, Inria/ENS
    Marc Pouzet, LIENS

S2.3 Compositional Timing-Aware Semantics for Synchronous Programming
    Joaquin Aguado, University of Bamberg
    Michael Mendler, University of Bamberg
    Jiajie Wang, University of Auckland
    Partha Roop, University of Auckland
    Bruno Bodin, University of Edinburgh
 
 


 

Session 3: Programming Languages for Quantum Computing
 
Presentations by:
 
3.1 Benoît Valiron, CentraleSupelec, University Paris-Saclay
 
3.2 Nader Khammassi, TU Delft
 
3.3 Michael Kirkedal Thomsen, University of Copenhagen
 
 


 
Session 4: Design and Validation Methodologies
 
4.1 Automatic Generation of Cycle-Accurate Simulink Blocks from HDL IPs
    Stefano Centomo, University of Verona
    Michele Lora, University of Verona
    Antonio Portaluri, EDALab
    Francesco Stefanni, EDALab
    Franco Fummi, University of Verona    

4.2 An Innovative Methodology to Check Consistency Between HDL and UPF Descriptions
    Arthur Kalsing, TIMA Laboratory
    Laurent Fesquet, TIMA Laboratory
    Chouki Aktouf, Defacto Technologies

4.3 Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
    Vladimir Herdt, University of Bremen
    Hoang M. Le, University of Bremen
    Daniel Grosse, University of Bremen & DFKI
    Rolf Drechsler, University of Bremen

 


 

Session 5: Next Generation Many-Cores

S5.1 Language and Hardware Acceleration Backend for Graph Processing
    Andrey Mokhov, Newcastle University
    Alessandro de Gennaro, Newcastle University
    Ghaith Tarawneh, Newcastle University
    Jonny Wray, e-Therapeutics
    Georgy Lukyanov, Southern Federal University
    Sergey Mileiko, Newcastle University
    Joe Scott, Newcastle University
    Alex Yakovlev, University of Newcastle
    Andrew Brown, University of Southampton

S5.2 Runtime Task Mapping for Lifetime Budgeting in Many-Core Systems
    Terrence Mak, University of Southampton

S5.3 A Reconfigurable Bit-serial FFT/FIR Processor for Ultra-low-power Applications
    Yue Lum, University of Southampton
    Tom Kazmierski, University of Southampton
 
 


 

Session 6: Design, Optimization, and Verification of Modern Industry Applications

6.1 Identifying Bottlenecks in Manufacturing Systems Using Stochastic Criticality Analysis
    Joao Bastos, Eindhoven University of Technology
    Bram van der Sanden, Eindhoven University of Technology
    Olaf Donk, ICT Group
    Jeroen Voeten, Eindhoven University of Technology
    Ramon Schiffelers, Eindhoven University of Technology
    Sander Stuijk, Eindhoven University of Technology
    Henk Corporaal, Eindhoven University of Technology

6.2 ASIL Decomposition Using SMT
    Mona Safar, Ain Shams University

6.3 Multi-Objective Optimization-based Development of Power Electronics for Automotive Applications
    Jonas Stricker, Universität der Bundeswehr München

6.4 An Emulation Framework for Closed Source Components in Multi-core Automotive Platforms
    Ignacio Sanudo, University of Modena and Reggio Emilia
    Paolo Burgio, University of Modena and Reggio Emilia
    Marko Bertogna, Univerity of Modena

 


Work-In-Progress Session

WiP1 Error Propagation for Cascading Metamodels Applied on an Electric Drive Application
    Christine Forster, Infineon
    Manuel Harrant, Infineon
    Jerome Kirscher, Infineon

WiP2 From SQL to Database Processors: A Retargettable Query Planner
    Arda Yurdakul, Bogazici University

WiP3 An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL)
    Tobias Strauch, EDAptix

WiP4 Towards MARTE++: An Enhanced UML-based Language to Model and Analyse Real-Time and Embedded Systems for the IoT Age
    Julio Medina, Universidad de Cantabria
    Eugenio Villar, Universidad de Cantabria

WiP5 Scalar Replacement with Array Dataflow Analysis for Hardware Synthesis
    Kenshu Seto, Tokyo City University

WiP6 Operational Computation of Uncertain Analog Systems Using Orthogonal Parameters
    Leandro Gil, University of Stuttgart
    Martin Radetzki, University of Stuttgart
 
 


 

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