FDL 2017 Advance Program with Timing

Share it now


Monday - September 18
 
8:30 AM - 9:00 AM    Registration
 

9:00 AM - 10:30 AM    Hands-on Tutorial 1

Exploiting Automatic Abstraction and the FMI Standard to Build Cycle-Accurate Virtual Platforms from Heterogeneous IPs
Organizer: Michele Lora, University of Verona, Italy

Abstract: A major problem when designing complex systems is the vast set of different design domains to consider. Usually, each design domain is managed by one or more team of engineers strongly specialized on the particular domain. Each team usually relies on the best-suited set of tools and techniques for modeling and simulating the components of the system the team must design. For this reason, a major obstacle to achieve holistic system simulation is the impossibility to connect different tools and heterogeneous models.
The Functional Mock-up Interface (FMI) Standard aims at tackling this problem by defining a standardized interface to connect different simulators and models.
Another emerging approach addresses the issues introduced by the heterogeneity by reconciling heterogeneous models to an intermediate homogeneous representation. The approach relies on automatic translation and abstraction techniques to achieve such a target.
This tutorial combines the automatic abstraction features provided by HIFSuite, and the interfacing functions furnished by the FMI Standard, to create a cycle-accurate virtual platform of an HW/SW device. The tutorial will start with a set of heterogeneous Intellectual Property (IP) components, representing both digital and analog devices. Each IP will be translated and abstracted to produce a "basic block" of an FMI-based simulation environment:  a Functional Mock-up Unit (FMU). Then, the tutorial will show how to use PyFMI, an open-source Python-based FMI Simulator, to integrate the produced FMUs to create the final model for the holistic simulation of the system. Finally, the tutorial will show how to use the obtained simulation environment when aiming at developing embedded SW running on the modeled HW platform.
Participants will work directly on a case study composed of a general purpose CPU connected to a set of heterogeneous peripherals, ranging from HW accelerators to an analog accelerometer. They will learn how to exploit the FMI Standard to integrate heterogeneous models to describe an HW/SW device. Furthermore, they will learn how to use PyFMI to create simulation scenarios composed by multiple FMUs. Tools utilized in the tutorial are open-source (PyFMI) or licensed by EDALab s.r.l. (HIFSuite). EDALab will donate HIFSuite for teaching, training and research purpose to participants at the end of the tutorial.

10:30 AM - 11:00 AM    Coffee
 

11:00 AM - 12:30 PM    Hands-on Tutorial 2
Introduction to SPARK~2014 -- How to Develop Ultra-Low Defect Software

Organizer: Martin Becker, Technische Universitat Munchen, Germany

Abstract: This tutorial aims at giving a practical, hands-on introduction to SPARK 2014, a modern, imperative and object-oriented programming language, specifically conceived for the development and formal verification of high-integrity software.
We cover basic features of the language, such as data types, concurrency and contracts, and then apply static verification to prove the correctness of contracts, as well as the absence of run-time errors (such as overflows, division by zero or even race conditions). Further topics include the inclusion of legacy code, the combination of testing and static analysis, the precision of numerical operations, and a brief outlook on secure programming for data-sensitive applications. We close the tutorial with an example of how these tools can be used in a practical setting.

Prerequisites:
Participants should bring a laptop with GNAT GPL and SPARK GPL installed (download for free from http://libre.adacore.com/download/), to be able to follow the exercises.

12:30 PM - 1:30 PM    Lunch
1:30 PM - 2:00 PM    Opening Session (Franco Fummi)
 
2:00 PM - 3:00 PM    Keynote 1:
IoT Trends and Innovative Applications (Roberto Zafalon)
 
3:00 PM - 3:30 PM    Coffee
 
3:30 PM - 5:00 PM    Session 1:
Modelling and Simulation

Chair: Julio Medina
 
1.1 Fault Analysis in Linear Analog Circuits through Language Manipulation and Abstraction

    Enrico Fraccaroli, University of Verona
    Franco Fummi, University of Verona
    Francesco Stefanni, EDALab
    Mark Zwolinski, University of Southampton

 
1.2 Actor Fission Transformations for Executing Dataflow Programs on Manycores
    Essayas Gebrewahid, Halmstad University
    Zain Ul-Abdin, Halmstad University

 
1.3 Rethinking of I/O-Automata Composition
    Sarah Chabane, University M’Hamed Bougara
    Rabea Ameur-Boulifa, Université Paris-Saclay
    Mohamed Mezghiche, University M’Hamed Bougara

 
5:00 PM - 6:00 PM  Panel 1:
The WHAT? and WHY? of High-Level Languages in Designing and Verifying Complex Integrated Systems
Moderator: Sara Bocchio, STMicroelectronics

Speaker 1: Nigel Woolaway, Leading Edge
Nigel Woolaway received his Bachelors degree in Communications Engineering from the University of Kent at Canterbury in 1981 after which he held various roles in design engineering working on optical communication systems and primary digital multiplexors for telecommunication systems. While working at STC in 1984 he was an early adopter of EDA in the form of the Valid SCALD system. He joined STMicroelectronics (then SGS) in 1985 where he subsequently became engineering workstation manager, responsible for the development of design kits for the Daisy, Mentor and Valid platforms. Nigel subsequently worked for Mentor Graphics (4 years), Synopsys (9 years) and Magma Design Automation (1 year) before joining forces with Pietro Vergine to form Leading Edge in 2005. Nigel is currently co-President of Leading Edge, an Italian SME providing design, verification and training services to the European design community as well as technical and commercial representation for a number of innovative EDA providers.

Speaker 2: Daniel Große, University of Bremen
Daniel received the Dr.-Ing. degree in computer science from the University of Bremen, Germany, in 2008. He remained as postdoctoral researcher in the group of Computer Architecture in Bremen. In 2010 he was a substitute professor for computer architecture at Albert-Ludwigs University, Freiburg, Germany. From 2013 to 2014 he was CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015 he is a senior researcher at the University of Bremen and the German Research Center for Artificial Intelligence (DFKI) Bremen and also the scientific coordinator of the graduate school System Design (SyDe), funded within the German Excellence Initiative. His research interests include verification, high-level languages, virtual prototyping, debugging and synthesis. In these areas he published more than 80 papers in peer-reviewed journals and conferences and served in program committees of numerous conferences like e.g. DATE, ICCAD, CODES+ISSS.

Speaker 3: Massimo Roselli, Cadence Design Systems
Massimo Roselli is a Digital Design & Verification Application Engineer at Cadence Design System with 19 years’ experience in Electronic Design Automation. Prior to Cadence, he worked as a Digital Designer and Verification Engineer for Galileo Avionica (Leonardo). He holds Master of Engineering degree in Microelectronic from Università degli Studi di Roma “Tor Vergata”. Massimo has a deep knowledge of System on Chip and IP Verification with advanced testbench, Debug, Low Power Design and Verification. He knows all common languages used for RTL Design and Verification including property specification languages. Massimo also has over 16 years of experience in Formal Verification. He closely collaborates with Cadence R&D and customers on developing new tools and methodologies particularly in the context of Formal Verification.

6:00 PM - 7:00 PM   Welcome Reception


 
Tuesday - September 19
 
8:30 AM - 9:30 AM  Keynote 2:
Programming in a Heterogeneous World (Jan Kuper)
 
9:30 AM - 11:00 AM  Session 2:
Languages and Design Methods for Time-critical Systems

Chair: Daniel Grosse
 
2.1 Real-Time Ticks for Synchronous Programming

    Reinhard von Hanxleden, Christian-Albrechts-Universität zu Kiel
    Timothy Bourke, INRIA, PARKAS Team
    Alain Girault, INRIA, SPADES Team

 
2.2 Symbolic Simulation of Dataflow Synchronous Programs with Timers
    Guillaume Baudart, ENS
    Timothy Bourke, Inria/ENS
    Marc Pouzet, LIENS

 
2.3 Compositional Timing-Aware Semantics for Synchronous Programming
    Joaquin Aguado, University of Bamberg
    Michael Mendler, University of Bamberg
    Jiajie Wang, University of Auckland
    Partha Roop, University of Auckland
    Bruno Bodin, University of Edinburgh

 
11:00 AM  - 11:30 AM Coffee
 
11:30 AM  - 1:00 PM  Session 3:
Programming Languages for Quantum Computing

Chair: Kenshu Seto
 
3.1 Benoit Valiron, CentraleSupelec, Univ. Paris-Saclay
3.2 Nader Khammassi, TU Delft
3.3 Michael Kirkedal Thomsen, University of Copenhagen
 
1:00 PM  - 2:00 PM   Lunch
 
2:00 PM  - 3:00 PM   Panel 2
 
3:00 PM  - 4:00 PM   WIP Session + Posters
 
WiP1 Error Propagation for Cascading Metamodels Applied on an Electric Drive Application

    Christine Forster, Infineon
    Manuel Harrant, Infineon
    Jerome Kirscher, Infineon

 
WiP2 From SQL to Database Processors: A Retargettable Query Planner

    Arda Yurdakul, Bogazici University
 
WiP3 Towards MARTE++: An Enhanced UML-based Language to Model and Analyse Real-Time and Embedded Systems for the IoT Age

    Julio Medina, Universidad de Cantabria
    Eugenio Villar, Universidad de Cantabria

 
WiP4 Scalar Replacement with Array Dataflow Analysis for Hardware Synthesis

    Kenshu Seto, Tokyo City University
 
 
4:00 PM  - 4:30 PM   Coffee
 
4:30 PM  - 6:00 PM   Session 4:
Design and Validation Methodologies

Chair: Tom Kazmierski
 
4.1 Automatic Generation of Cycle-Accurate Simulink Blocks from HDL IPs

    Stefano Centomo, University of Verona
    Michele Lora, University of Verona
    Antonio Portaluri, EDALab
    Francesco Stefanni, EDALab
    Franco Fummi, University of Verona    
 
4.2 An Innovative Methodology to Check Consistency Between HDL and UPF Descriptions
    Arthur Kalsing, TIMA Laboratory
    Laurent Fesquet, TIMA Laboratory
    Chouki Aktouf, Defacto Technologies
 
4.3 Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
    Vladimir Herdt, University of Bremen
    Hoang M. Le, University of Bremen
    Daniel Grosse, University of Bremen & DFKI
    Rolf Drechsler, University of Bremen
 
6:00 PM  - 10:00 PM    Social Event

 
 
Wednesday - September 20
 
8:30 AM  - 9:30  AM    Keynote 3:
Do Design/Specification Languages Have Any Role to Play in Cyber-Security?
(Sandeep Shukla)
 
9:30 AM  - 11:00 AM Session 5:
Next Generation Many-Cores

Chair: Nicola Bombieri
 
5.1 Language and Hardware Acceleration Backend for Graph Processing

    Andrey Mokhov, Newcastle University
    Alessandro de Gennaro, Newcastle University
    Ghaith Tarawneh, Newcastle University
    Jonny Wray, e-Therapeutics
    Georgy Lukyanov, Southern Federal University
    Sergey Mileiko, Newcastle University
    Joe Scott, Newcastle University
    Alex Yakovlev, University of Newcastle
    Andrew Brown, University of Southampton

5.2 Runtime Task Mapping for Lifetime Budgeting in Many-Core Systems
    Terrence Mak, University of Southampton

5.3 A Reconfigurable Bit-serial FFT/FIR Processor for Ultra-low-power Applications
    Yue Lu, University of Southampton
    Tom Kazmierski, University of Southampton

 
11:00 AM  - 11:30 AM   Coffee
 
11:30 AM  - 1:30 PM    Session 6:
Design, Optimization, and Verification of Modern Industry Applications

Chair: Ashraf Salem
 
6.1 Identifying Bottlenecks in Manufacturing Systems Using Stochastic Criticality Analysis

    Joao Bastos, Eindhoven University of Technology
    Bram van der Sanden, Eindhoven University of Technology
    Olaf Donk, ICT Group
    Jeroen Voeten, Eindhoven University of Technology
    Ramon Schiffelers, Eindhoven University of Technology
    Sander Stuijk, Eindhoven University of Technology
    Henk Corporaal, Eindhoven University of Technology

6.2 ASIL Decomposition Using SMT
    Mona Safar, Ain Shams University
 
6.3 Multi-Objective Optimization-based Development of Power Electronics for Automotive Applications

    Jonas Stricker, Universität der Bundeswehr München

6.4 An Emulation Framework for Closed Source Components in Multi-core Automotive Platforms
    Ignacio Sanudo, University of Modena and Reggio Emilia
    Paolo Burgio, University of Modena and Reggio Emilia
    Marko Bertogna, Univerity of Modena

1:30 PM    Closing
 
 


 

Share it now