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ESLsyn 2015 Program

Wednesday, June 10

11:00-12:00 Welcome Coffee
12:00-12:15 Welcome
12:15-13:00 Keynote 1: Achim Rettberg, Hella KGaA, Germany
13:15-13:30 Coffee Break
13:30-15:00 Session 1
15:00-15:30 Coffee break
15:30-16:30 Invited Talk: Yuko Hara-Azumi, Tokyo Institute of Technology
16:30-17:30 Panel discussion
18:00-20:00 Social Event: Dinner

 

Thursday, June 11

10:00-11:00 Keynote 2: Forrest Brewer, UCSB
11:00-12:00 Session 2
12:00-13:00 Lunch
13:00-14:00 Invited talk : Ben Carrion Schafer, Hong Kong Polytechnic University
14:00-15:15 Session 3
15:15-16:00 Panel discussion

 

Wednesday, June 10

11:00-12:00

Welcome Coffee

12:00-12:15

Introduction

General Chair:
Jörn Janneck, Lund University, Sweden

Co-Chair:
Achim Rettberg, Hella KGaA, Germany

Industrial Chair:
Andres Takach, Calypto

Program Chair:
Zhiru Zhang, Cornell University, Computer Systems Laboratory, Ithaca, NY, USA

12:15-13:15


Keynote 1 : Achim Rettberg, Hella KGaA, Germany

New Challenges and Solutions for System Synthesis

 

13:15-13:30 Coffee break
13:30-15:00

Session 1: 
Adaptive Combined Macro and Micro-Exploration of Concurrent Applications mapped on shared Bus Reconfigurable SoC
Yidi Liu and Benjamin Carrion Schafer, Hong Kong Polytechnic University (Hong-Kong)

Performance Analysis of Wallace and Radix-4 Booth-Wallace Multipliers
Shahzad Asif and Yinan Kong, Macquerie University (Australia) 

evercodeML: a formal language for SoC integration
José Ignacio Villar De Ossorno, Jorge Juan, David Guerrero Martos, Manuel Jesus Bellido and Julian Viejo, Escuela Técnica Superior de Ingeniería Informática, Sevilla (Spain)

15:00-15:30 Coffee break
15:30-16:30


Invited Talk: Yuko Hara-Azumi, Tokyo Institute of Technology

Partially-Programmable Circuit: New Flexible Method for Fault-Tolerance Improvement and Its Application

State-of-the-art devices including downscaled CMOS and post-silicon devices are facing to the high failure rate severely. While conventional approaches, employing (partial) redundancy of the original circuit, worked well for the case that the failure rate is quite low, they are no longer useful for such new, unreliable devices, wherein redundancy would be more extensively required. In this talk, we present a set of our recent works to address this issue by partially-programmable circuit (PPC), a novel, flexible circuit which replaces part of ASICs with reconfigurable Look-Up Tables (LUTs). PPCs are unique in that they have no switches unlike FPGAs, but may bypass failure (detected by LSI tests) only by reconfiguring the LUTs and using redundant wires inserted in advance. Assuming stuck-at-faults on the wires and gates in the circuit, we present synthesis methods of PPCs which achieve better area-efficiency for improving fault tolerance than conventional methods. Also, we will show other possible ways of leveraging PPCs and their applied example in ESL synthesis.

Bio
Yuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. She was a JSPS postdoctoral research fellow at Ritsumeikan University from 2010 to 2012, during which she was also a visiting scholar at University of California, Irvine, USA and Karlsruhe Institute of Technology, Germany. In 2012, she joined Nara Institute of Science and Technology, as an assistant professor. Since 2014, she has been with the Graduate School of Science and Engineering, Tokyo Institute of Technology, where she is currently an associate professor. Her research interests include system-level design automation, especially on high-level and logic synthesis, for embedded/dependable systems. She currently serves as organizing and program committees of several premier conferences including ICCAD, DATE, ASP-DAC, RTCSA, and so on.

16:00-17:30

Panel Discussion

18:00-20:00

Social Event: Dinner

   

Thursday, June 11

10:00-11:00


Keynote 2 : Forrest Brewer, University of California, Santa Barbara

Trends and Open Problems in High Level Synthesis

High level synthesis has been an up-and-coming technology since the 80s, yet much of the promise seems to remain distant. Like all CAD techniques, tools follow industrial demands, but recuring conceptual and practical issues hamper adoption as well as research in this area. This talk reflects on the trends and successes of system synthesis, as well as some low-hanging open problems. 

Bio

Forrest Brewer earned a BS in Physics in 1980, spent several years as an engineer and then earned a Ph.D. in Computer Science at the University of Illinois in 1988. As a graduate he created a very early high level synthesis tool 'Chippe' that made RT-level designs from a Pascal-like input language. Chippe was the first such too to support automated code and hardware pipelining using an expert-system hill climbing technique. With A. Seawright, he created PBS, an extended regular automata based synchronous language particularly suited to interface protocol design, the tool later became the underlying technology in Synopsys' Protocol Compiler. In later years, Prof. Brewer introduced Symbolic Scheduling with I. Radivojevic and S. Haynal, a technique particularly suited to exact or high quality control dominated design. The tool was used at Intel to verify microcode performance for floating point Itanium libraries. More recently, he has worked in the area of mixed-signal VLSI in constrained environments such as cryogenic, radiation hard, and low power real-time. With G. Hoover, he built an attributed grammar synthesized for asynchronous system design and more recently made forays into extending the scale of high quality scheduling and constraint maintenance from thousands to millions of nodes. He is currently working on rad-hard asynchronous links and related IP to be used in the CMS experiment for the Large Hadron Collider at CERN

11:00-12:00

Session 2: 

Towards Hierarchical Scheduling of Dependent Systems with Hypervisor-based Virtualization
Jan Jatzkowski C-LAB, University of Paderborn (Germany)
Marcio Kreutz UFRGS – Institute of Informatics Porto Alegre (Brazil)
Achim Rettberg Carl von Ossietzky University Oldenburg 26129 Oldenburg (Germany)

Modeling SystemVerilog Assertions using SysML and CCSL
Aamir M. Khan, University of Buraimi (Oman)
Frédéric Mallet, Université Nice Sophia Antipolis (France)
Muhammad Rashid, Umm Al-Qura University (Saudi Arabia)

 
12:00-13:00 Lunch
13:00-14:00


Invited Talk 2: Benjamin Carrion Schafer, Hong Kong Polytechnic University

Behavioral IPs Micro-architectural Diversity and its Applications

C-based VLSI design has some distinct advantages over traditional RT-level design flows. One of these advantages is the ability to generate different micro-architectures with unique area vs. performance trade-offs without having to modify the original behavioral description.
This talk reviews the main exploration knobs that allow the design space exploration of behavioral descriptions and continues by describing different applications domains where these micro-architectural diversities can be applied to. In particular in HW security for third party intellectual property protection (3PIPP), logic emulation and finally fault tolerance.

Bio
Dr. Benjamin Carrion Schafer received the B.Eng. degree in Electrical and Electronic Engineering from the Polytechnic University of Madrid, Spain, the M.Sc. degree in Microelectronics from Birmingham City University, U.K., and FH-Darmstadt, Germany. After completing his Ph.D. at the University of Birmingham, U.K., he worked in the Computer Science Department at the University of California Los Angeles (UCLA) as a Postdoctoral Researcher from 2003 to 2004. He then joined the School of Electronic Engineering and Computer Science at Seoul National University, Korea, as a Visiting Research Scholar from 2005 to 2007. From 2007 until September 2012, he was working as a researcher at NEC Corporation, System IP Core Department, Central R&D Center, Kawasaki, Japan.  Since 2012 he works as an assistant professor at the Hong Kong Polytechnic University.
Dr. Carrion Schafer has been engaged in the research and development of VLSI systems, reconfigurable computing, thermal-aware VLSI design and High Level Synthesis (HLS). He served on the TPC of CASES 2006 and as a committee member at the RECONFIG, DAC (user track) and ESLSyn, FPL and ASP-DAC conferences. He was also a member of OSCI's (Accellera) SystemC synthesizable user group committee. He holds an MBA from McGill University.

14:00-15:15

Session 3: 

Process Selection for Maximum Resource Sharing in High-Level Synthesis

Benjamin Carrion Schafer, Hong Kong Polytechnic University (Hong-Kong)

From System Modeling to Formal Verification
Ajay Chhokra, Sherif Abdelwahed, Abhishek Dubey, Sandeep Neema and Gabor Karsai, Vanderbilt University (USA)

15:15-16:00

Panel Discussion


 

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