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ESLsyn 2014 Program
Click on the link in the table for the session description.

Saturday, May 31

09:00-09:45 Registration
09:45-10:00 Welcome to ESLsyn
10:00-11:00 Keynote 1: Lech Jozwiak, Eindhoven University of Technology, The Netherlands
11:00-12:00 Session 1: Application Analysis
12:00-13:00 Lunch
13:00-14:00 Keynote 2: Jorn W. Janneck, Lund University, Sweden
14:00-15:30 Session 2: Work in Progress
15:30-16:00 Coffee Break
16:00-17:30 Panel Discussion
18:00-20:00 Social Dinner


Sunday, June 1

09:00-09:45 Invited Talk 1: Kazutoshi Wakabayashi, NEC
09:45-10:30 Invited Talk 2: Andres Takach, Calypto
10:30-11:00 Coffee Break
11:00-12:00 Session 3: High-Level Synthesis
12:00-13:00 Lunch
13:00-14:00 Invited Talk 3: Andy Pimentel, University of Amsterdam, The Netherlands
14:00-15:30 Session 4: System-Level Synthesis


Saturday, May 31




Welcome to ESLsyn

General Chair:
Achim Rettberg, University of Oldenburg, Germany

Program Co-Chairs:
Benjamin Carrion Schafer, Hong Kong Polytechnic University, China
Christian Haubelt, University of Rostock, Germany



Keynote 1:
Lech Jozwiak, Eindhoven University of Technology, The Netherlands

Architecture Synthesis of Heterogeneous MPSoCs for Highly-Demanding Applications

The spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a very complex multi-processor system on a single chip (MPSoC) and facilitated a rapid progress in mobile and autonomous computing, global networking and wire-less communication. Numerous new sorts of embedded and cyber-physical systems became technologically feasible and economically justified. Various monitoring, control, communication or multi-media systems that can be put on or embedded in (mobile, poorly accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern cyber-physical applications are very complex, heterogeneous, and impose very stringent functional and parametric demands. The combination of the huge complexity with the stringent application requirements results in numerous serious design and development challenges, such as: accounting in design for more aspects and related complex multi-objective MPSoC optimization, adequate resolution of numerous complex design tradeoffs, reduction of the design productivity gap, reduction of the time-to market and development costs without compromising the system quality, etc. These challenges cannot be well addressed without an adequate system and design methodology adaptation. The presentation discusses the serious issues and challenges in the development of contemporary and future demanding embedded systems. Subsequently, it introduces the Intel's ASIP-based MPSoC technology and discusses a new automatic design flow for heterogeneous ASIP-based MPSoCs, when focusing on the system and procesor level design-space exploration (DSE). This flow and its EDA tools are results from the European research project ASAM (Automatic Architecture Synthesis and Application Mapping for MPSoCs based on adaptable ASIPs) performed in the framework of the European industrial research program ARTEMIS. The final presentation part overviews several methods and EDA-tools of the ASAM flow focusing on the micro-architecture level DSE involving the application analysis and parallelization, ASIP micro-architecture synthesis and application scheduling and mapping, combined in one coherent HW/SW co-synthesis process.

Lech Jóźwiak received his M. Sc. and Ph. D. degrees from the Faculty of Electronics, Warsaw University of Technology, Poland, in 1976 and 1982, correspondingly. From 1976 he has been continuously working in the area of his specialization in academia, research institutes or industry in Poland, The Netherlands, USA, Canada and Australia. Currently he is an Associate Professor, Head of the Section of Digital Circuits and Formal Design Methods, in the Department of Electronic Systems, Eindhoven University of Technology, The Netherlands. He is an author of the methodology of quality-driven system design, information-driven approach to digital circuit synthesis, and theories of information relationships and measures, and general decomposition of discrete relations that have both a theoretical value and considerable practical importance. He is also a creator of several practical products in the fields of embedded systems and EDA tools. He is an author of more than 180 journal and conference papers, some book chapters, and presenter of numerous keynotes and tutorials at international conferences and summer schools. He is an Editor in Chief of the journal of “Microprocessors and Microsystems”, Director of EUROMICRO, Founder and Steering Committee Chair of the EUROMICRO Conference on Digital System Design, Advisory Committee and Organizing Committee member of the IEEE International Symposium on Quality Electronic Design; and program committee member of many other conferences. He is or was an advisor and consultant to the industry, Ministry of Economy, and Commission of the European Communities. He was a recipient of multiple Letters and Diplomas of Recognition for highly esteemed services and exceptional achievements from a. o. the Minister of Economy of Poland, presidents of professional societies and organizations (e.g. IEEE, EUROMICRO, ISQED, etc.) and chief editors of international scientific journals (e.g. IEEE Transactions on Computers; IEEE Transactions on CAD, etc.). In 2008 he was a recipient of the Honorary Fellow Award of the International Society of Quality Electronic Design for “Outstanding Achievements and Contributions to Quality of Electronic Design”.


Session 1: Application Analysis
Accelerating Full-System Simulation ESL Design and Application Analysis through Multi-Granularity and Focused Profiling
Tzu-Hsiang Su (Macronix International Co., Ltd. & National Chiao Tung University), Wei-Shan Wu, Chen-Te Chou, Yuan-Chun Cheng, Meng-Ting Tsai and Tien-Fu Chen (National Chiao Tung University)

Precise Deadlock Detection for Polychronous Data-flow Specifications
Chan Ngo, Jean-Pierre Talpin and Thierry Gautier (INRIA-IRISA Centre Rennes-Bretagne Atlantique)




Keynote 2:  Jorn W. Janneck, Lund University, Sweden

Wither High-Level Synthesis?

High-level synthesis describes a collection of technologies for deriving implementations from abstract descriptions of a system. As a field, its success record has been mixed, in spite of undeniable progress on many fronts. Rather than focusing on the technical issues that remain to be solved, this talk will try to look at some of the opportunities for our field, and speculate about possible directions it might take. How can high-level synthesis be more relevant, and to whom, and for what? And how does it relate to other developments in adjoining fields, especially software development for highly parallel computing machines?

Jorn W. Janneck is an associate professor in the computer science department at Lund University. He graduated from the University of Bremen in 1995 and received a PhD from ETH Zurich in 2000. He worked at the Fraunhofer Institute for Material Flow and Logistics (IML) in Dortmund, was a postdoctoral scholar at the University of California at Berkeley in the EECS department, and worked in industrial research from 2003 to 2010, first at Xilinx Research in San Jose, CA, and more recently at the United Technologies Research Center in Berkeley, CA. He is one of the authors of the CAL actor language and has been working on tools and methodology focused on making dataflow a practical programming model in a wide range of application areas, including image processing, video coding, networking/packet processing, DSP and wireless baseband processing. He has made major contributions to the standardization of RVC-CAL and dataflow by MPEG and ISO. His research is focused on aspects of programming parallel computing machines, including programming languages, machine models, tools, code generation, profiling, and architecture.


Session 2: Work in Progress

A Memory-First Language and Model for Hardware-Software Cosynthesis
Kunal Arya and Forrest Brewer (University of California, Santa Barbara, USA)

An Assisted Single Source Verification Metric Model Code Generation Methodology
Christoph Kuznik, Gilles Bertrand Defo, and Wolfgang Mueller (University of Paderborn, Germany)

Automated Implementation of Operand Isolation on Netlists
Matthias Sauppe, Thomas Horn, Erik Markert, Ulrich Heinkel (TU Chemnitz, Germany), and Klaus-Holger Otto (Alcatel-Lucent AG, Nuremberg, Germany)


Coffee Break


Panel Discussion


Social Dinner


Sunday, June 1


Invited Talk 1: Kazutoshi Wakabayashi, NEC

FPGA+HLS: New computing Paradigm for Complex Algorithm Synthesis

This paper discusses how FPGA with High Level Synthesis can change computation mechanism for control flow intensive algorithm, which has many conditional branches, conditional jump (goto). Control dependencies have been obstacles for high performance computing, or automatic parallelization, for CPU, GPGPU and also for RTL-based design hardware. However, our HLS, called CyberWorkBench, can parallelize CDFG based only on data dependencies and control dependencies are not obstacles for parallelization in scheduling. Therefore, when C program is compiled into FPGA with HLS, its performance is much better than CPU and GPGPU and even RTL-based design hardware. In this case, FPGA+HLS could be thought as a special processor customized for a single C program. This paper discusses the difference among processor, RTL-based hardware and FPGA+HLS using FMSD model, and illustrate how control dependencies are neglected for parallelization. This paper also shows some examples FPGA+HLS is used, su ch as high frequency trading(HFT), CODEC, motor control.


Kazutoshi Wakabayashireceived his B.E. and M.E. degrees and Dr. of Engineering from the University of Tokyo in 1984 and 1986. He was a visiting researcher at Stanford University during 1993 and 1994. He joined NEC Corporation in Kawasaki Japan in 1986 and he is currently a Senior Manager of EDA R&D Center, Central Research Labs. Dr.Wakabayashi has been engaged in the research and development of VLSI, CAD systems; high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floorplan links, and reconfigurable computing. He served on executive committee or organizing committee of some international conference including: ASP-DAC'09 General Chair, CODES+ISSS'09 Co-Technical Program Chair. A Secretary of Steering Committee of ASP DAC, and Asian Rep. of ICCAD, Asian Rep. of DAC, Tutorial Chair of ASP DAC 2006, He has served on the program committees for several international conferences including: DAC, ICCAD, DATE, ASP-DAC, ISSUS, SASIMI, and ITC-CSCC, ISCAS, VLSI-TSI and SBCCI. Also, he has served as a general chair, a secretary, and a Technical Program Committee member for a number of Japanese conferences, including: Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ), System LSI WS, Karuizawa WS. He is currently chair of SIG on VLSI design methodology of IEICE, and elected member of IEICE. He was an associate editor of Transactions on IEICE on VLSI CAD, DAEM. He is a rep. of CEDA (Council for EDA) of IEEE. He is also a member of IEEE, IPSJ, and IEICE. He received the Yamazaki-Teiichi Prize in 2004, and the IPSJ Convention Award in 1988, Sakai Kinen Special Award in 2001, and the NEC Distinguished Contribution Award in 1993 for his logic synthesis system, in 1999 for his formal verification and in 2006 for his High Level Synthesis system. His C-based Synthesis and Verification tool suite called "CybeWorkBench" received a Grand prize of "LSI of the Year 2003" and "LSI of the Year 2007".


Invited Talk 2: Andres Takach, Calypto

HLS Current State, Adoption Drivers, and Future Directions

Industry adoption of high-level synthesis has been steadily growing in the last few years especially for designs in communication and image and video processing.

The increasing design complexity is adding momentum to the wider adoption of HLS as a way to reduce the ever increasing cost of verification. This includes verification of the high-level models written in C++ or SystemC, verifying that the RTL generated by HLS is correct compared to the high-level models as well as integrating into and evolving within existing SoC verification methodologies.

HLS has also shown advantages for lowering power of designs at the high level by enabling quick exploration of the effects of architectural decisions, performing power specific optimizations at higher levels than RTL, and by facilitating the job of downstream RTL power optimizations tools.

This talk will cover the state of HLS, the drivers for adoption and the emerging requirements in terms of standards, verification, power optimization, and integration with existing RTL flows and methodologies.

Senior architect and R&D manager working on Calypto's high-level synthesis and its integration with Calypto's Verification and Power optimization products.He chairs Accellera's SystemC Synthesis Working Group. Prior to joining Calypto, he was Chief Scientist at Mentor Graphics where he worked since 1997 on high-level synthesis. From 1993 to 1997, he was Professor at Illinois Institute of Technology where he conducted research on HLS and Hardware/Software Co-design. Dr. Takach holds a Ph.D. degree from Princeton University and MSEE and BSEE degrees from the University of Wisconsin-Madison.


Coffee Break


Session 3: High-Level Synthesis

Machine-Learning based Simulated Annealer method for High Level Synthesis Design Space Exploration
Anushree Mahapatra and Benjamin Schafer (The Hong Kong Polytechnic University, China)

A Hierarchical Framework to Enhance Scalability and Performance of Scheduling and Mapping Algorithms
Wei Tang and Forrest Brewer (University of California, Santa Barbara, USA)




Invited Talk 3: Andy Pimentel, University of Amsterdam, The Netherlands

Perspectives on System-level MPSoC Design Space Exploration

The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of the field of system-level design and synthesis. To cope with the design complexity, system-level design and synthesis methods aim at raising the abstraction level of the design process. Key enablers to this end are, for example, the use of architectural platforms to facilitate re-use of IP components and the notion of high-level system modelling and simulation. The latter allows for capturing the behavior of platform components and their interactions at a high level of abstraction. As such, these high-level models minimize the modeling effort and are optimized for execution speed, and can therefore be applied during the very early design stages to perform design space exploration.  Such early design space exploration is of paramount importance as early design choices heavily influence the success or failure of the final product. In this talk, I will provide an overview of the recent advances in our research on system-level MPSoC design space exploration and will present some future challenges that need to be addressed in this domain.

Full bio at
Andy Pimentel is associate professor at the University of Amsterdam, where he leads the Computer Systems Architecture group. He holds the MSc and PhD degrees in computer science, both from the University of Amsterdam.  His research focuses on system-level embedded systems design, and in particular on methods for system-level design space exploration. More specifically, his research interests include system-level modelling and simulation, design space pruning, performance and power analysis, workload modelling, MultiProcessor System-on-Chip (MPSoC) systems, computer architecture, and parallel and reconfigurable computing. Andy is co-founder of the International Conference on embedded computer Systems: Architectures, Modelling, and Simulation (SAMOS).  He is associate editor of Elsevier's Simulation Modelling Practice and Theory and Springer's Journal of Signal Processing Systems. Andy Pimentel has published more than 100 scientific papers, book chapters and editorials. Moreover, he has served on the organizational committees for many leading (embedded) computer systems design conferences and workshops, such as DAC, DATE, CODES+ISSS, ICCAD, ICCD, FPL, SAMOS, and ESTIMedia. He will be General Co-chair of HiPEAC’15 and Local Organizing Co-chair of ESWeek’15. He is Senior member of the IEEE and select member of IFIP WG 10.3.


Session 4: System-Level Synthesis

Considering Variation and Aging in a Full Chip Design Methodology at System Level
Domenik Helms, Kim Gruettner, Reef Eilers, Malte Metzdorf, Kai Hylla, Frank Poppen (OFFIS - Institute for Information Technology, Germany), and Wolfgang Nebel (Carl von Ossietzky University Oldenburg, Germany)

Coarse Grain Clock Gating of Streaming Applications in Programmable Logic Implementations
Endri Bezati, Simone Casale Brunet, Marco Mattavelli (EPFL, Switzerland), and Jorn W Janneck (Lund University, Sweden)

System Level Synthesis of Many-Core Architectures using Parallel Stream Rewriting
Lars Middendorf and Christian Haubelt (University of Rostock)

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