Electronic System Level Synthesis Conference
ESLsyn 2012 Proceedings
The 2012 Electronic System Level Synthesis Conference
June 2-3, 2012
San Francisco, California, USA
49th ACM/EDAC/IEEE Design Automation Conference, June 3-7, 2012
at the Moscone Center in San Francisco, CA
The ESLsyn 2014 proceedings are available to ECSI members, conference attendees and presenters. Contact us to get your credentials.
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ESLsyn 2012 Program (public)
ESLsyn 2012 Proceedings (public)
ISBN - ECSI Media
ISBN - IEEE Xplore Compliant PDF Files
Stephen Edwards, Columbia University
Keynote 2: A Fresh Look at High Level Synthesis (restricted access)
Satnam Singh, Google
Keynote 3: High-level Synthesis: Where We Are and How We Got Here (restricted access)
John Sanguinetti, Forte DS
Keynote 4: Challenges and Opportunities of Behavioral Level SoC Design (restricted access)
Benjamin Carrion Schafer, NEC
Michael McNamara, Cadence
Arkadeb Ghosal, National Instruments
Special Session on Virtual Platform
Towards Performance and Energy Efficient Embedded System Design using Virtual Platforms (restricted access)
Achim Rettburg, University of Oldenburg/OFFIS
Design Space Exploration (restricted access)
Vittorio Zaccaria, Politecnico di Milano - PoliMi
EDA Synthesis Tools Presentations
Session 1: High Level Synthesis
Trimmed VLIW: Moving Application Specific Processors Towards High Level Synthesis
Janarbek Matai, Jason Oberg, Ali Irturk, Taemin Kim, and Ryan Kastner
We describe a synthesis methodology called Trimmed VLIW, which we argue lies between application specific processors and high level synthesis. Much like application specific processors, our methodology starts from a known instruction set architecture and customizes it to create the final implementation. However, our approach goes further as we not only add custom functional units and define the parameters of the register file, but we also remove unneeded interconnect, which results in a data path that looks more similar to that created by high level synthesis tools. We show that there are substantial opportunities for eliminating unused resources, which results in an architecture that has significantly smaller area. We compare area, delay and performance results of a base architecture with trimmed one. Preliminary results show by only trimming wires we have an average of 25% area reduction while improving the performance around 5%. Furthermore, we evaluated our results with highlevel synthesize tools C2V and AutoESL.
A Model-Based Inter-Process Resource Sharing Approach for High-Level Synthesis
of Dataflow Graphs
Christian Zebelein, Joachim Falk, Christian Haubelt, and Jürgen Teich
High-level synthesis tools are gaining more and more acceptance in industrial design flows. While they increase productivity in implementing a single complex hardware module, synthesizing and optimizing many hardware components simultaneously is still an open problem. In particular, resource sharing is typically only performed for single components, thereby neglecting optimization possibilities across concurrent modules. On the other hand, domain-specific models and specifications, which are generally seen as a key ingredient to raise the level of abstraction in future design flows, may enable such global optimizations. In this paper, we present a model-based approach for inter-process resource sharing which provides for efficient high-level synthesis of streaming applications modeled as a set of communicating processes. The applicability of the proposed approach is validated by a case study.
Session 2: Modelling
Synthesizing Embedded Software with Safety Wrappers through Polyhedral Analysis in a Polychronous Framework
Mahesh Nanjundappa, Matthew Kracht, Julien Ouy, and Sandeep Shukla
Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how integrating a Satisfiability Modulo Theory (SMT) solver to POLYCHRONY compiler can enhance its decision making capabilities. Further, we show, how a polyhedral analysis library integrated to the compiler, can compute safe operational boundaries, and filter unsafe input combinations to keep the system safe. We enhanced the POLYCHRONY compiler’s ability to make more accurate decisions and to accept and characterize the safe input range for specifications where safety may be violated for a relatively small region of a large input space. The enhancement also allows the user to consider the severity of the violation with respect to entire space of inputs, and either reject a specification or synthesize a wrapped software with guaranteed safe operation.
Session 3: High-Level Synthesis
Transaction-Accurate Interface Scheduling in High-Level Synthesis
John Sanguinetti, Michael Meredith, and Sean Dart
The timing model for code presented to a high-level synthesis tool is an important factor in determining the level of abstraction which the HLS tool can support. There have been many attempts at defining a timing model. Here we survey some of the timing models that have been used, and present the transaction protocol model, used by Forte Design Systems’ Cynthesizer, which has several advantages over previous timing models.
Enabling Tools for Virtual Platforms
Virtual platforms are gaining attention for the development and validation of embedded software before the corresponding hardware is available. Transaction-level modelling (TLM) is the most promising technique to develop virtual platforms. However, modelling a complex system completely at transaction level could be a challenging task. This paper presents recent developments done by EDALab to simplify the creation of TLM virtual platforms. In particular, it describes 1) a methodology and a tool to generate TLM models from IP cores described at register transfer level (RTL) or by using model-driven design tools such as Matlab/Stateflow, 2) a SystemC/TLM library to simulate packet-based communications outside the system in case of networked embedded systems.
Slides (restricted access)
Session 4: MPSoCs
Multi-layer Configuration Exploration of MPSoCs for Streaming Applications
Deepak Mishra, Yasaman Samei, Nga Dang, Rainer Doemer, and Elaheh Bozorgzadeh
While integration of configurable components, such as soft processors, in MPSoC design enables further system adaptation to application needs, supporting system level tools need to provide an environment for systematic and efficient configuration exploration. This paper presents a multi-layer configuration exploration framework for streaming applications on MPSoCs. We introduce a novel Configuration Exploration Tree (CET) for configuration selection per processor. Integrated in a system-level design environment, our CET enables efficient and fully automatic exploration of processor configurations in MPSoC. The proposed CET supports the fast evaluation of feasible configurations by simulation at highest levels of abstraction. In addition, assuming monotonous impact of configuration values on system throughput, we use an ordering among the nodes in the CET to minimize necessary simulations. Our exploration efficiently finds all feasible configurations for a given constraint.
Process Variation-aware Task Replication for Throughput Optimization in Configurable
Love Singhal, Hessam Kooti, and Eli Bozorgzadeh
Due to within-die and die-to-die variations, multiple cores in MPSoC have different delay distributions, and hence the problem of assigning tasks to the cores become challenging. This paper targets system level throughput optimization in streaming pipelined MPSoCs under process variation. First, to maximize system level throughput, we make extensive use of data parallelism of the streaming applications to map them to multiple cores available on a chip. In order to tackle the effect of process variation in clock frequency of these cores, and the resulting deterioration in system timing yield, we propose to deploy frequency scaling and configuration selection for each core. We incorporate timing yield constraint during task replication and load balancing for data parallel tasks. The novel contribution of this work is that we perform all these operations simultaneously, and show the benefits of our approach. We present an ILP solution for maximum throughput under process variation and the proposed solution determines the right degree of parallelism at target timing yield. Our proposed ILP formulation is very generic and can be used for task replication of single or multiple tasks, while simultaneously performing optimum load balancing. The results show that the MPSoC system design flows that do not consider one or more than one of the above mentioned design decisions simultaneously, suffer greatly from the design failures and fail to meet strict timing yield and bandwidth constraints. The throughput of such an MPSoC system is also worse than half of the throughput of our proposed system.
List of ESLsyn 2012 Participants (restricted access)