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The 2012 Electronic System Level Synthesis Conference

June 2-3, 2012
San Francisco, California, USA

co-located with DAC!
49th ACM/EDAC/IEEE Design Automation Conference, June 3-7, 2012
at the Moscone Center in San Francisco, CA

EDA Synthesis Solutions


Cadence Design Systems, Inc.
C-to-Silicon Compiler
Cadence C-to-Silicon Compiler synthesizes high-level SystemC TLM to RTL. Because it is the only high-level synthesis tool that embeds production RTL synthesis, it can perform more aggressive optimizations for better quality of results with the confidence that the generated RTL will still meet timing downstream in logic synthesis. This is why the RTL generated by C-to-Silicon usually meets or beats the quality of results of hand-written RTL, which is vital for use in designing production hardware.
C-to-Silicon Compiler can also be run in incremental mode, to minimize changes to resulting RTL when you need to accommodate an Engineering Change Order (ECO). This ECO capability is automatically coupled with Cadence's Conformal ECO technology to deliver the industry's only TLM-to-GDSII ECO flow.
Cadence has partnered with customers to develop and deploy a full production design and verification flow that begins with SystemC TLM, truly raising the entry point of design and verification and delivering faster time to verified RTL.






National Instruments

LabVIEW DSP Design Module (
LabVIEW DSP Design for the LabVIEW FPGA Module reduces the complexity of designing real-time DSP subsystems for high-speed field-programmable gate array (FPGA) applications such as RF and communications. Using a stream-based graphical abstraction, you can rapidly implement an algorithm, explore design trade-offs, and generate an optimized FPGA implementation. You can then integrate the resulting implementation as a modular part of a larger LabVIEW FPGA-based application. 

  • Rapidly prototype real-time FPGA-based digital signal processing (DSP) subsystems
  • Seamlessly integrate rich FPGA-based math and signal processing libraries
  • Design your own signal processing blocks and import third-party IP blocks
  • Explore design trade-offs early in the design process

LabVIEW FPGA IP Builder (
LabVIEW FPGA IP Builder augments the capabilities of the LabVIEW FPGA design platform, allowing you generate high-performance field-programmable gate array (FPGA) IP by combining high-level synthesis (HLS) technology with the power of LabVIEW graphical development and NI FPGA-based hardware.
With LabVIEW FPGA IP Builder, user-provided directives capture design constraints that guide its code generator, so you do not have to learn hardware description languages (HDLs) or more advanced LabVIEW FPGA optimization concepts. Instead, the tool uses state-of-the-art HLS technology to apply pipelining, resource multiplexing, loop unrolling, and others techniques in order to generate resource- and timing-optimized FPGA IP. With the LabVIEW FPGA IP Builder, you can match or exceed the results obtained through manual LabVIEW FPGA design optimization and use your time to focus on the high-level design of your algorithms. Because design directives are stored separately from algorithm code, you can quickly explore design trade-offs and reuse IP to meet new design requirements.



The primary objective of COMPLEX is to develop an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of embedded HW/SW systems. Complex will focus on early, fast yet accurate platform-based design space exploration at the system level.

The COMPLEX consortium develops a new design environment for platform-based design-space exploration offering developers of next-generation mobile embedded systems a highly efficient design methodology and tool chain. The integrated environment allows iterative exploration and refinement of advanced applications to meet market requirements. The design technology in particular enables fast simulation and assessment of the platform at Electronic System Level (ESL) with up to bus-cycle accuracy at the earliest instant in the design cycle. The main objectives are:

  • Highly efficient and productive design methodology and holistic framework for design space exploration of embedded HW/SW systems. The resulting framework will be platform vendor and application domain independent, provide open interfaces for a later integration of new industry players.

  • Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping from a combined HW/SW perspective

  • Interfacing next-generation model-driven SW design approach and industry standard model-based design environments.

  • Multi-objective co-exploration for assessing design quality and to optimize the system platform with respect to performance, power, and reliability metrics.

  • Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.

  • Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.



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