ESLsyn 2011 Proceedings

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The 2011 Electronic System Level Synthesis Conference

June 5-6, 2011
San Diego, California, USA

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ESLsyn 2011 Program (public)

ESLsyn 2011 Proceedings (public)

ESLsyn 2011 Proceedings on IEEE Xplore

BibTex of ESLsyn 2011 Proceedings

ISSN 2117-4628


Print ISBN

Dr. Adam Morawiec
Jinnie Hinderscheit

European Electronic Chips & Systems design Initiative

Parc Equation - 2, Avenue de Vignate
38610 Gières, France
office [at] ecsi [dot] org

Keynote 1: Rethinking your Assumptions in ESL Design (restricted access)

Rishiyur S. Nikhil, Bluespec

Keynote 2: The Codependent Relationship of High-Level Synthesis and Verification (restricted access)

Michael McNamara, Cadence Design Systems

Keynote 3: ESL Model Refinement Challenges (restricted access)

Andres Takach, Mentor Graphics

Keynote 4: Synthesis of Distributed Real-Time Embedded Software (restricted access)

Edward Lee, University of California, Berkeley

Invited Presentation: Quo Vadis ESL? (restricted access)

Dan Gajski, University of California, Irvine


EDA Synthesis Tools Presentations

C-to-Silicon Compiler Incremental Synthesis Cadence’s C-to-Silicon Compiler’s Quality of Results (restricted access)

Michael McNamara, Cadence Design Systems

Catapult C Synthesis Overview (restricted access)

Andres Takach, Mentor Graphics

High-Level Synthesis for Systems in FPGAs (restricted access)

Stephen Neuendorffer, Xilinx


Panel Discussion: ESL Synthesis? Get Real!!! (restricted access)


Session 1: Co-design – Part I

A Hardware/Software Co-design Template Library for Design Space Exploration
Peter Brunmayr, Jan Haase, and Christoph Grimm

The ability to map a high level algorithm either to hardware or software simplifies design space exploration of cyber-physical systems. Thereby, low level tools can be utilized for accurate design parameter estimation, which helps to evaluate the effect of system level design decisions. Especially complex data structures pose a problem in this context. The different structure of memory in hardware and software requires different data structure implementations. With the presented data structure library a consistent design flow from a high level system model to either a hardware or software implementation is enabled. The concept extends the idea of abstract data types across the hardware/software boundary. Container adapters with appertaining implementations for system level simulation, hardware and software implementation support the designer throughout the whole design process. The benefit of the presented library is demonstrated and evaluated by a case study. With very little effort seven different hardware solutions were generated and compared concerning their power consumption and their resource usage.

Paper (public)          Slides (restricted access)          IEEE Xplore

Unifying Process Networks for Design of Cyber Physical Systems
Christoph Grimm and Jiong Ou

Design of cyber-physical systems poses new challenges. Design at the level of a whole cyber-physical system includes design issues such as formal and abstract specification, design space exploration, optimization, and verification. A particular challenge is the formal and abstract representation of whole cyber-physical systems including both physical and cyber components. The objective of this paper is to show ways to unify process networks in order to enable representation of cyberphysical systems within the above mentioned design issues.

Paper (public)          Slides (restricted access)          IEEE Xplore

Session 2: FPGAs and Synthesis – Part I

Just-in-Time Compilation for FPGA Processor Cores
Andrew Becker, Scott Sirowy, and Frank Vahid

Portability benefits have encouraged the trend of distributing applications using processor-independent instructions, a.k.a. bytecode, and executing that bytecode on an emulator running on a target processor. Transparent just-in-time (JIT) compilation of bytecode to native instructions is often used to increase application execution speed without sacrificing portability. Recent work has proposed distributing FPGA circuit applications in a SystemC bytecode to be emulated on a processor with portions possibly dynamically migrated to custom bytecode accelerator circuits or to native circuits on the FPGA. We introduce a novel JIT compiler for bytecode executing on a soft-core FPGA processor. During an iterative process of JIT compiler and emulator architecture codesign, we added JIT-aware resources on a soft-core processor’s surrounding FPGA fabric, including a JIT memory, a signal queue, and an emulation memory controller—all unique to JIT compilation for FPGA processors versus traditional processors. Experiments show that regular JIT compilation achieved 3.0x average speedup over emulation, while our JIT-aware FPGA resources yielded an additional 5.2x average speedup, for a total of 15.7x average speedup, at a cost of 21% of a MicroBlaze processor core’s slice usage.

Paper (public)          Slides (restricted access)          IEEE Xplore

FPGA-Specific Optimizations by Partial Function Evaluation
Henning Manteuffel, Cem Savas Bassoy, and Friedrich Mayer-Lindenberg

Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.

Paper (public)          Slides (restricted access)          IEEE Xplore

Session 3: Modelling

System Synthesis from AADL Using Polychrony
Yue Ma, Huafeng Yu, Thierry Gautier, Jean-Pierre Talpin, Loic Besnard, and Paul Le Guernic

The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for systemlevel co-design; use the formal framework Polychrony, based on the synchronous language SIGNAL, for analysis, validation and synthesis. According to SIGNAL’s polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.

Paper (public)          Slides (restricted access)          IEEE Xplore

SCiPX: A SystemC To IP-Xact Extraction Tool
Jean-François Le Tallec and Robert De Simone

The IP-Xact formalism (IEEE 1685 standard), was introduced to help assemble IP components from distinct sources into an integrated design. Components would be expressed in high-level HDLs such as SystemC, and so should be the full design after composition. Currently, while components exist at SystemC level, they generally do not provide any local IP-Xact structural interface representation. The present contribution studies the difficulties in creating such an IPXact interface declaration from SystemC, solves most of them, and provide SystemC modeling guidelines so that a richer set of informations can be recovered and reported into IP-Xact.

Paper (public)          Slides (restricted access)          IEEE Xplore

From Design-Time Concurrency to Effective Implementation Parallelism: The Multi-Clock Reactive Case
Virginia Papailiopoulou, Dumitru Potop-Butucaru, Yves Sorel, Robert De Simone, Loic Besnard, and Jean-Pierre Talpin

We have defined a full design flow starting from highlevel domain specific languages (Simulink, SCADE, AADL, SysML, MARTE, SystemC) and going all the way to the generation of deterministic concurrent (multi-threaded) executable code for (distributed) simulation or implementation. Based on the theory of weakly endochronous systems, our flow allows the automatic detection of potential parallelism in the functional specification, which is then used to allow the generation of concurrent (multi-thread) code for parallel, possibly distributed implementations.

Paper (public)          Slides (restricted access)          IEEE Xplore

Session 4: Co-design – Part II

A Framework for Generic HW/SW Communication Using Remote Method Invocation
Philipp A. Hartmann, Kim Grüttner, Philipp Ittershagen, and Achim Rettberg

Implementation of communication between different tasks of a concurrent embedded system is a challenging problem. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underlying middleware or embedded operating system. Moreover, communication should also be transparent accros the HW/SW boundary. In this work we present a generic framework for seamless communication of (software) tasks with shared resources, called Shared Objects. Communication is implemented using a method-based interface realizing a Remote Method Invocation (RMI) protocol. Our shared communication resources can either be implemented as dedicated hardware, as shared memory or local tasks. The presented framework is a first step towards the unification of shared resource access based on embedded Linux. The effectiveness of our approach is be evaluated with different task mappings and shared resource access implementation styles.

Paper (public)          Slides (restricted access)          IEEE Xplore

Kahn Process Networks Applied to Distributed Heterogeneous HW/SW Cosimulation
Dylan Pfeifer and Jonathan Valvano

Heterogeneous, distributed hardware/software cosimulation techniques using the backplane method encounter complex interface protocols for simulator communication and synchronization, limiting their adoption or abstraction. We simplify the dynamics of backplane cosimulation to the properties of a Kahn Process Network (KPN), such that tokens of the KPN are interpolated events. This simplifies the backplane API and reduces the coordination problem to a parameterization of token update rates. The performance of this method is reported on a timed ISS model for Freescale HC12 microcontrollers (TExaS) coordinated with a Spice (Ngspice) circuit simulation.

Paper (public)          Slides (restricted access)          IEEE Xplore

Session 5: FPGAs and Synthesis – Part II

Enabling the Synthesis of Very Long Operation Properties
Jan Langer, Thomas Horn, and Ulrich Heinkel

In previous work, the high-level synthesis of operation properties has been proposed. In this work, we improve the existing algorithms in order to allow the synthesis of more efficient hardware models. Especially for very long properties no model could be generated before, because both the runtime of the synthesis process and the amount of used hardware resources were prohibitively high.

The proposed improvements are threefold. First, the generated non-deterministic control automaton is replaced by a deterministic automaton using an optimized power set construction algorithm. This significantly reduces the number of registers in the generated model. Second, a property can contain local variables (freeze variables), that capture a value at a specific time step and provide this value throughout a property’s life span. The scheduling of storage registers for these variables has been optimized. The last improvement merges equivalent assignments to output or state variables (commitments). The merging avoids not only the generation of redundant hardware resources but also simplifies the output multiplexer of the model.

Finally, a case study is presented that involves an industrial design of a framer component. The design properties describe the processing of a complete data frame of 19440 cycles length. High-level synthesis and subsequent logic synthesis have been successful and show that the design methodology and synthesis algorithms result in a design with resource usage similar to the industrial component.


Paper (public)          Slides (restricted access)          IEEE Xplore


Increasing Computational Density of Application-Specific Systems
Michael Wilder and Robert Rinker

Application-specific systems are increasingly being deployed on reconfigurable computing platforms such as the field-programmable gate array (FPGA). These systems can integrate many disparate computing elements, and often contain soft processors hosting application components. Soft processors are sequential, synchronous devices with low computational density, and are not capable of exploiting the concurrency available on the FPGA.

We present a method for increasing the computational density of application-specific systems by eliminating soft processors within these systems. This method eliminates soft processors by replacing programs that would be hosted on soft processors with custom, selfcontained, circuitizable finite-state machine with datapath (FSMD) components that are automatically generated. We show that FSMDs produced using this method eliminate the computational overhead associated with fetching and decoding instructions. We further show that this method, when applied to interrupt-driven programs, can produce concurrent FSMDs that arbitrate for shared datapath resources.

We discuss how these FSMDs are capable of leveraging the spatial computational capabilities of the FPGA and are therefore more aptly suited for deployment within application-specific systems. We show that these FSMDs eliminate overhead associated with interrupt context switching, decrease interrupt servicing latencies, and eliminate interrupt livelock. We discuss implications and limitations of this method, and describe a prototype that implements the method for programs targeted for the Intel 8051.

aper (public)          Slides (restricted access)          IEEE Xplore


Session 6: System Design

Application-Specific Co-design Platform Generation for Digital Mockups in Cyber-Physical Systems
Bailey Miller and Frank Vahid, Tony Givargis

The testing of cyber-physical systems requires validating device functionality for a wide range of operating conditions. The environment with which the cyber-physical device interacts, such as lungs for a medical ventilator device or a busy freeway for an autonomous vehicle, may be complex and subsequently difficult to explore all possible configurations. Computer simulations that utilize device and environment behavioral models may be used as a first stage of testing, but at some point development must occur using the real device running in real-time. We present a codesign framework for aiding cyber-physical device development where real devices or prototypes are connected to real-time models that simulate the interacting environment. Such test setups are known as digital mockups and allow for testing environment scenarios that are hard to capture with commonly-used but limited physical mockups. The framework supports model hardware/software codesign to enable models of varying speed and accuracy to be implemented within an embedded processor or as a custom coprocessor circuit on an FPGA. We describe an accompanying tool that generates code templates to reduce the time required to develop digital mockup test setups. We utilize the framework to build a digital mockup test setup for a commercial ventilator, and showcase codesign capabilities by implementing environmental models as both circuits and as instructions on a processor.

Paper (public)          Slides (restricted access)          IEEE Xplore

A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes
Srikrishna Iyer, Jingyao Zhang, Yaling Yang, and Patrick Schaumont

Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low-power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/software codesign for sensor node application development. We present the integration of nesC, a sensornet programming language, with GEZEL, an easy-to-use hardware description language. We describe the hardware/software interface at different levels of abstraction: at the level of the design language, at the level of the co-simulator, and in the hardware implementation. We use a layered, uniform approach that is particularly suited to deal with the heterogeneous interfaces typically found on small embedded processors. We illustrate the strengths of our approach by means of a prototype application: the integration of a hardware-accelerated crypto-application in a nesC application.

Paper (public)          Slides (restricted access)          IEEE Xplore


ESLsyn 2011 List of Participants (restricted access)

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