Electronic System Level Synthesis Conference
Call for Contributions
The 2011 Electronic System Level Synthesis Conference
June 5-6, 2011
San Diego, California, USA
General Chair: Dan Gajski, University of California, Irvine
Co-Chair & Organization: Adam Morawiec, ECSI
Program Co-Chairs: Philippe Coussy, Lab-STICC, Université de Bretagne Sud and Sandeep K. Shukla, Virginia Tech University
Rishiyur S. Nikhil, Bluespec
Rethinking your assumptions in ESL Design
Andres Takach, Mentor Graphics
ESL Model Refinement Challenges
Edward Lee, University of California, Berkeley
Synthesis of Distributed Real-Time Embedded Software
Michael McNamara, Cadence Design Systems
The Codependent Relationship of High-Level Synthesis and Verification
Dan Gajski, University of California, Irvine
Quo Vadis ESL?
The ever increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementation are needed for designing both HW and SW parts.
The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cycle time all together, breaking the trend to compromise on the evaluation of various design implementation options. Designing at higher levels of abstraction is a viable way to better cope with the system design complexity, to verify earlier in the design process and to increase code reuse.
The Electronic System Level Synthesis Conference ESLsyn focuses on automated system design methods that enable efficient modelling of systems to provide the capability to synthesize HW platforms and embedded software with particular aspects related to synthesis.
This conference will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in the domain of ESL synthesis. It will give an outline of synthesis methods and tools available currently in the market and discuss their applicability, performance, strengths and user experiences. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users, but also will be a forum to discuss scientific concepts and paradigms for the future evolution of synthesis methods.
Cyber-Physical System/System/Platform: model-driven synthesis, models of computation, virtual prototyping, design space exploration, design methodologies, architectures, co-design, interface synthesis, partitioning, performance analysis, optimization, modeling refinement, transformation, generation, languages, formal specification and verification methods, virtualization, target platforms: ASIC, FPGA, GPU, many- & multi-core, SOC platforms, HW accelerators, …
High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis for HW Design: hierarchical synthesis, algorithmic transformations, loop transformations, scheduling & binding techniques, correctness, formal verification, reliability, incremental synthesis, control-oriented synthesis, low-power synthesis, performance-driven synthesis, target-specific synthesis, multiple clock design, input languages & subsets, internal representation, interaction with low-level synthesis, certification, trade-off analysis, …
Embedded Software Synthesis: programming models (including multi-core, GPU programming models), correct-by-construction software synthesis, intermediate representations, scheduling techniques, binding, communication and synchronization protocols, middleware/hardware-dependent software, performance analysis and optimization, domain-specific languages and methods (AADL etc.), concurrent program synthesis, compilers for multi-/many- cores, time triggered vs. event triggered models, synchronous programming models, formal methods for embedded software design and verification, …
The above list is not an exhaustive list of topics addressed by ESLsyn; contributions related to ESLsyn problems in general not listed here are highly welcome. Submissions may be theoretical scientific papers, research in progress, case studies, tool use cases and best practice, as well as industry experiences.
Authors should submit their full papers (up to 6 pages, double-column IEEE format) in PDF through the web based submission system. Submitted papers should be anonymous, are required to describe original unpublished work and must not be under consideration for publication elsewhere. The conference proceedings will be published in electronic form with the ISSN number and made available in the ECSI Resource Center. Full submission requirements, templates and submission page link can be found at www.ecsi.org/eslsyn/submissions. The selected best papers from several ESLsyn Conference editions will be published in the book edited by SPRINGER.
Paper submission deadline:
April 14, 2011 (extended) Paper submission is now closed
Notification of acceptance: May 15, 2011
Camera ready papers: May 22, 2011
ESLsyn 2011 is organized with the technical co-sponsorship of
IEEE Council on Electronic Design Automation (CEDA)