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DASIP 2014

Conference on Design & Architectures for Signal & Image Processing

October 8-10, 2014
Madrid, Spain


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DASIP 2014 Program
Click on the links in the table to see the descriptions of the sessions.

Wednesday, October 8

08:15    09:00 Registration
09:00    09:30     Opening Session
09:30    10:30     Keynote 1
10:30    11:30    Coffee Break and Poster Session 1
11:30    12:45    Session 1
12:45    14:15   Lunch
14:15    15:55    Session 2
15:55    16:40    Coffee Break and Poster Session 2*
16:40    17:30    Session 3*
18:30    21:30   Demo Night

* Special Sessions - Best Paper Candidates

Thursday, October 9

08:30    09:00     Registration
09:00    10:00     Keynote 2
10:00    11:00    Coffee Break and Poster Session 3
11:00    12:40   Session 4*
12:40    14:10  Lunch
14:10    15:50   Session 5
15:50    16:35   Coffee Break
21:00    23:30    Conference Dinner and Social Event

* Special Sessions - Best Paper Candidates

Friday, October 10

09:30    10:30     Keynote 3
10:30    11:00    Coffee Break
11:00    12:40   Session 6
12:40    13:00 Closing Session

METODO Workshop program

DASIP 2014 Program

Wednesday, October 8

08:15    09:00     Registration
09:00    09:30     Opening Session
09:30    10:30     Keynote 1

Invasive Computing - Principles and Benefits
Speaker: Jürgen Teich
Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

Abstract: Technology roadmaps foresee 1000 and more processors being integrated in a single MPSoC in the year 2020. For such systems, the control of multiple concurrent applications can obviously not be organized in a fully centralized way any more as it is done today.
In this talk, we present present <invasive computing> as a new paradigm for an application-driven, decentralized as well as resource-aware organization of concurrent applications on future large scale MPSoCs.
The main goal of invasive computing is to provide scalable efficiency and
at the same time more predictability of parallel computing on multi-core systems including execution time, power and safety aspects.
Conceptually, efficiency may be raised if temporal computational needs
of an application may be translated into a dynamic reservation of exclusive resources.
The result of an invasion phase is a so-called claim of resources. After termination of a computationally demanding execution phase, the application may release the resources again back to the pool in a phase called retreat.
Through the exclusiveness of provided resources including not only processors, but also memory access and communication bandwidth on a network on chip, a much higher predictability of non-functional properties shall become possible as well.

In the talk, we provide results of the DFG-funded collaborative reseach center
TR89 on invasive computing including a) a language definition and implementation for invasive computing based on X10 as developed by IBM.
Moreover, we will show how invasive programs may be b) efficiently
simulated so to have a testbed for invasive application developers, resource-aware programming, and design space exploration of architectural
tradeoffs such as numbers and types of processors, and memory organization. Finally, c) a real-time video application is used to show that predictable throughput processing may be achieved on invasive massively parallel target architectures called tightly-coupled processor arrays (TCPAs) even for varying number of available processors at run-time by exploiting and proposing a claim-dependent selection of video processing algorithm to be executed as a QoS tradeoff with image quality.

BIO: Jürgen Teich (Senior Member, IEEE) received the M.S. degree
(Dipl.-Ing.; with honors) from the University of Kaiserslautern,
Germany, in 1989 and the Ph.D. degree (summa cum laude) from the
University of Saarland, Saarbruecken, Germany, in 1993.  In 1994, he
joined the DSP design group of Prof. E. A. Lee in the Department of
Electrical Engineering and Computer Sciences (EECS), University of
California at Berkeley (PostDoc). From 1995 to 1998, he held a position
at the Institute of Computer Engineering and Communications Networks
Laboratory (TIK), ETH Zurich, Switzerland (Habilitation).  From 1998 to
2002, he was Full Professor in the Electrical Engineering and
Information Technology Department, University of Paderborn, Germany.
Since 2003, he has been Full Professor in the Department of Computer
Science, University of Erlangen-Nuremberg, Erlangen, Germany, holding a
chair in Hardware/Software Co-Design.  In 2011, he was elected member of
the Academia Europaea. Since 2010, he has also been the coordinator of
the Transregional Research Center 89 on Invasive Computing funded by the
German Research Foundation (DFG).


10:30    11:30   

Coffee Break and Poster Session 1

Model-Driven design flow for distributed control in reconfigurable FPGA systems
Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah and Jean-Luc Dekeyser.

Energy-Aware Decoders: a Case Study Based on an RVC-CAL Specification
Rong Ren, Eduardo Juarez, Cesar Sanz, Mickael Raulet and Fernando Pescador.

HLS-based FPGA Implementation of a Predictive Block-based Motion Estimation Algorithm - A Field Report
Gregor Schewior, Christian Zahl, Holger Blume, Stefan Wonneberger and Jan Effertz.

Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors
Christian Hochberger, Lukas Johannes Jung, Andreas Engel and Andreas Koch.

11:30    12:45   

Session 1

Wearable Computing, Compressed Sensing, and Communication
Chair: Johan Lilius
Abo Academy, Finland


Communication capacity and speed are constantly increasing. This development is enabled by the increased available computational capacity and advancements in algorithmics. We have however reached a point where we need to start considering novel solutions to algorithms, archtectures, communication media and sensing approaches. This session will contribute by demonstrating a new transmitter for photonics applications that is capable of providing 10Gb/s net rate over low-cost optical circuits, a new compressed sensing algorithm that achieves minimal energy consumption, and a sensor system based on neural networks that is applicable to human activity recognition.

Rakeness-based Compressed Sensing on Ultra-Low Power Multi-Core Biomedical Processors.
Daniele Bortolotti, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti and Luca Benini.

A Wereable Human Activity Recognition System on a Chip.
Koldo Basterretxea, Javier Echanobe and Inés Del Campo.

Flexible Real-Time Transmitter at 10Gbit/s for SCFDMA PONs Focusing on Low-Cost ONUs.
Lukas Meder, Philipp Schindler, Amos Agmon, Maxim Meltsin, Rene Bonk, Michael Dreschmann, Joachim Meyer, Alex Tolmachev, Rolf Hilgendorf, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Jürg Leuthold, Christian Koos and Jürgen Becker.

12:45    14:15   Lunch
14:15    15:55    Session 2

Hardware, FPGAs, and Reconfigurable Hardware
Chair: Kevin Martin
Associate Professor U de Bretagne-Sud Lab-STICC

Abstract:Since their first appearence, FPGAs have been widely used, studied, and enhanced. It makes it an attractive component for low-volume devices, for prototyping, and for efficient implementation exploiting its parallelism features. The design on FPGA also relies on methods and tools that improve productivity in a convinient way. In this session, an FPGA implementation of a flexible synchronizer for cognitive radio applications is presented. An FPGA is used for prototyping memory controllers and predictive cache for image processing algorithms. A methodology and tool for automatic generation of data-flow based reconfigurable accelerators is presented and used for MPEG Reconfigurable Video Coding applications. A new soft-core is implemented in a Zynq to show the benefit of offloading operating system services.

FPGA Implementation of a Flexible Synchronizer for Cognitive Radio Applications.
Farid Shamani, Roberto Airoldi, Tapani Ahonen and Jari Nurmi.
Hardware Realization of an FPGA Processor -- Operating System Call Offload and Experiences.
Andreas Hindborg, Nicklas Bo Jensen, Pascal Schleuniger and Sven Karlsson.
Automatic Generation of Dataflow-Based Reconfigurable Coprocessing Units.
Carlo Sau and Francesca Palumbo.
Closed-loop Adaptive and Stochastic Prefetch Mechanism for Data Array.
Lionel Vincent and Stéphane Mancini.

15:55    16:40    Coffee Break and Poster Session 2 (Special Sessions)*

Arithmetic for Image and Signal Processing

Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP.
Judicael Menant, Muriel Pressigout, Luce Morin and Jean Francois Nezan.

Visual Scene Analysis on Hybrid Multicore

Antonio Fuentes-Alventosa, Juan Gómez-Luna, José María González-Linares and Nicolás Guil. CUVLE: Variable-Length Encoding on CUDA

Martin Danek, Roman Bartosinski and Christian Hochberger. Foreground Detection in Video Streams in an FPGA without External Memory

Matthieu Garrigues and Antoine Manzanera. Video++, a modern image and video processing C++ framework

16:40    17:30    Session 3 (Special Sessions)*

Arithmetic for Image and Signal Processing
Chair: Daniel Menard
Professor at INSA Rennes, FR
Co-Chair: Gabriel Caffarena
Associate Professor at University San Pablo CEU, ES

Abstract: Signal and Image and Processing (SIP) applications involve the execution of numerous mathematical operations. The aim of this session is to present  recent advances in the domain of architecture and arithmetic for SIP applications.
Applications in SIP domains are tolerant to overflows if their probability is small enough. In this context, determining the number of bits for the integer part of each fixed-point data is a trade-off between the implementation cost and the degradation of the application quality due to overflows. The first paper of the session proposes a new approach to accelerate the simulation of overflow effects by means of selective simulations .
Matrix inversion is a computationally intensive basic block of many SIP algorithms. In order to decrease the cost of their implementations, developpers often resort to fixed-point arithmetic. The second paper presents an automated approach to synthesize fixed-point code for matrix inversion based on Cholesky decomposition. In this context, the square root and division operators are analysed in terms of rounding error.

A Fast Method for Overflow Effect Analysis in Fixed-point Systems.
Riham Nehmeh, Daniel Menard, Andrei Banciu, Thierry Michel and Romuald Rocher.
Toward the synthesis of fixed-point code for matrix inversion based on Cholesky decomposition.
Matthieu Martel, Amine Najahi and Guillaume Revy.

18:30    21:30   Demo Night

Tomasz Kryjak, AGH U of Science and Technology, PL
Jorge Portilla, Universidad Politécnica de Madrid, ES
Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC on a Stereo Matching Application
Julien Heulot, Judicaël Menant, Maxime Pelcat, Jean Francois Nezan, Luce Morin, Muriel Pressigout and Slaheddine Aridhi.
Orcc’s Compa-Backend demonstration
Yaset Oliva, Emmanuel Casseau, Kevin Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin and Laurent Morin.
Robust Unclonable Identifiers and True Random Numbers from off-the-Shelf SRAMs
Miguel Ángel Prada Delgado, Susana Eiroa and Iluminada Baturone.
TURNUS: an open-source design space exploration framework for dynamic stream programs
Simone Casale Brunet, Malgorzata Maria Wiszniewska, Endri Bezati, Marco Mattavelli, Jorn Janneck and Massimo Canale.
A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time
Juan Valverde, Alfonso Rodriguez, Javier Mora, Jorge Portilla, Eduardo de La Torre and Teresa Riesgo.
Increased Fault Tolerance in Evolvable Hardware Through Automatic Upscaling
Javier Mora, Angel Gallego, Andrés Otero, Eduardo de La Torre and Teresa Riesgo.
Video surveillance algorithms implemented on the heterogeneous Zynq platform
Tomasz Kryjak, Mateusz Zun and Marek Gorgon.
Development of Brain-Computer Interfaces using Evolvable Hardware
Blanca Lopez, Javier Mora, Pablo Mansanet, Eduardo de La Torre and Teresa Riesgo.
The AhirV2 toolset for algorithm-to-hardware transformation. Madhav Desai.
MPEG High Efficient Video Coding Stream Programming and Many-Cores Scalability
Damien Jack De Saint Jorre, Daniele Renzi, Simone Casale Brunet, Malgorzata Maria Wiszniewska, Endri Bezati and Marco Mattavelli.

Thursday, October 9

08:30    09:00     Registration
09:00    10:00     Keynote 2

Adaptive Computing Systems: Current solutions and trends for the future
Speaker: Michael Hübner
Ruhr University Bochum, Germany

Abstract: Today ubiquitous computing is steadily growing in daily life, leading to an increasing need of resource awareness especially for devices with limited energy source. The running applications may differ significantly in their requirements and priority and these variations can occur during a single running application as well. Apart from the applications’ constraints, there
are regularly restrictions regarding the power source, which can vary during runtime. To tackle these issues, the design should focus on systems that can dynamically optimize themselves, according to the current requirements. Adaptive processors offer great advantages, such as the possibility to reconfigure the microarchitecture to specific needs online. Thus, it is possible
for the system to be optimized for each stage of the executing applications and the environmental conditions. The design space of adaptive systems is vast if many parameters can be adjusted during runtime. In order to develop and operate these systems, several different approaches must be taken into account.
In this talk, new design concepts are presented, together with a discussion of future trends in the field of adaptive processing systems.

BIO: Prof. Dr.-Ing. habil. Michael Hübner is the Chair for Embedded Systems for Information Technology (ESIT) at the Ruhr-University of Bochum (RUB) since April 2012. He received his diploma degree in electrical engineering and information technology in 2003 and his PhD degree in 2007 from the University of Karlsruhe (TH). Prof. Hübner did his habilitation in 2011 at the Karlsruhe Institute of Technology (KIT) in the domain of reconfigurable computing systems. His research interests are in reconfigurable computing and particularly new technologies for adaptive FPGA run-time reconfiguration and on-chip network structures with application in automotive systems, incl. the integration into high-level design and programming environments.

10:00    11:00    Coffee Break and Poster Session 3

A Review of World’s Fastest Connected Component Labeling Algorithms : Speed and Energy Estimation.
Laurent Cabaret, Lionel Lacassagne and Louiza Oudni.
Hardware Implementation of a Biometric Recognition Algorithm based on In-Air Signature.
Rosario Arjona, Iluminada Baturone and Rocío Romero-Moreno

Hardware Achitecture Design and Implementation for FMCW Radar Signal Processing Algorithm.
Eugin Hyun and Jonghun Lee.

0, 1, 2, Many - A Classroom Occupancy Monitoring System For Smart Public Buildings.
Francesco Paci, Davide Brunelli and Luca Benini.

Energy Consumption Modeling of Smart Nodes with a Function Approach.
Andriamampianina Aina Randrianarisaina, Olivier Pasquier and Pascal Chargé.

11:00    12:40   Session 4 (Special Session)*

Visual Scene Analysis on Hybrid Multicore
Chair: Lionel Lacassagne, Laboratoire de Recherche en Informatique (LRI) - INRIA Postale, FR

Abstract: Visual scene analysis is gaining interest in many applications, including medical, robotics, and driver assistance. Major challenges involve real-time techniques for visual scene analysis, on various levels of abstraction, from image data to higher level feature analysis.
The focus of this special session is on optimization techniques for hybrid multicore in embedded systems, including resource-aware programming, memory bandwidth optimization, hardware-software evaluation, and a scalable hardware approach.

Self Adaptive Harris Corner Detection on Heterogeneous Many-core Processor
Johny Paul, Walter Stechele, Éricles Rodrigues Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert and Tamim Asfour.
Optimizing Memory Bandwidth in OpenVX Graph Execution on Embedded Many-Core Accelerators
Giuseppe Tagliavini, Luca Benini and Germain Haugou.
Hardware-software implementation of vehicle detection and counting using virtual detection lines
Tomasz Kryjak, Mateusz Komorkiewicz and Marek Gorgon.
A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus Images.
Hamza Bendaoudi, Farida Cheriet, Houssem Ben Tahar and J.M.Pierre Langlois.

12:40    14:10  Lunch
14:10    15:50   Session 5

Frameworks and Model Transformations
Chair: Jean-Francois Nezan, Professor at INSA Rennes, IETR laboratory, FR

Abstract: The software productivity gap tends to increase with both hardware and software complexities. At the same time, new semiconductor technologies will come with an increase of the cost. This long term trend justifies the emergence of new tools to simplify the design process of embedded systems and to optimize the use of available resources in terms of execution time and power consumption. The session will give new results and original solutions to fill the productivity gap for signal and image processing applications.

A Framework for Rapid Prototyping of Embedded Vision Applications
Michael Mefenza, Franck Ulrich Yonga Yonga, Luca B. Saldanha and Christophe Bobda.

MARTE to πSDF transformation for data-intensive applications analysis.
Manel Ammar, Mouna Baklouti, Maxime Pelcat, Karol Desnos and Mohamed Abid.

Execution trace graph analysis of dataflow programs: bounded buffer scheduling and deadlock recovery using model predictive control
Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale and Jorn W Janneck.

Energy Efficiency and Performance Management of Parallel Dataflow Applications
Simon Holmbacka, Erwan Nogues, Maxime Pelcat, Sébastien Lafond and Johan Lilius.

15:50    16:35   Coffee Break
21:00    23:30    Conference Dinner

Friday, October 10

09:30    10:30     Keynote 3

Reconfigurable Data Stream Architectures in Industrial Audio Processing
Speaker: José Teixeira de Sousa
INESC-ID/IST, University of Lisbon, PT

Abstract: Digital audio requires algorithms for pre-processing, compression, decompression and post-processing. From a user perspective, smaller networked battery operated devices are increasingly used to record and play audio. From a provider perspective, audio over IP is rapidly expanding with broadcasters sending hundreds of encoded audio channels simultaneously. Pre and post-processing algorithms normally consist of Filtering and Equalizing. Common processing tasks are Sample Rate Conversion, Encoding, Decoding and Transcoding (decode and re-encode). A variety of algorithms exist for audio compression: MP1, MP2, MP3, Dolby digital, Dolby digital plus, AAC, HE-AAC, etc. These algorithms can be executed by general purpose processors (GPPs), digital signal processors (DSPs), specialized hardware blocks or a combination of the three. While GPPs and DSPs provide high flexibility and low risk in implementing audio systems, specialized hardware blocks provide the performance needed by many applications at the cost of a significant development schedule risk. Instruction-centric architectures are too slow and consume too much power in audio processing. In this talk we examine the use of data-centric or reconfigurable hardware blocks as a means to achieve the flexibility of software and the performance of hardware, while keeping silicon area small and power consumption low. An overview of commercial IP blocks for audio processing is presented, and our research at INESC-ID on a new architecture to address the limitations found in current approaches is outlined.

BIO: José T. de Sousa is professor of electrical and computer engineering at the University of Lisbon and a researcher at the INESC-ID institute in Lisbon, Portugal. From 2006 to 2013 he was CEO of Coreworks SA, a technology company designing silicon IP for audio processing. From 2004 to 2006 he served as principal engineer at Dafca, Inc, in Framingham, Massachusetts, a startup that created silicon debug infrastructure for systems on chip. He holds a PhD degree from Imperial College of Science and Technology, London University.


10:30    11:00    Coffee Break
11:00    12:40   Session 6

Heterogeneous Platforms
Chair: Walter Stechele
Professor at Technical University of Munich, Germany

Abstract: Heterogeneous platforms are gaining interest from many researchers due to their beneficial performance/power/cost ratio. However, heterogeneity imposes challenges on platform design, programmability, and runtime management. In this session, various aspects of heterogeneous platforms are investigated, including application mapping, parallelization strategies, on-chip communication, and FPGA-based prototyping.

Accelerating Local Feature Extraction using OpenCL on Heterogeneous Platforms
Konrad Moren, Diana Göhringer and Thomas Perschke.

PHAT: A Technology for Prototyping Parallel Heterogeneous Architectures
Thorsten Wink and Andreas Koch.

Low-Cost Guaranteed-Throughput Dual-Ring Communication Infrastructure for Heterogeneous MPSoCs
Berend Dekens, Philip Wilmanns, Marco Bekooij and Gerard Smit.

Communication-model based Embedded Mapping of Dataflow Actors on Heterogeneous MPSoC
Dinh-Thanh Ngo, Jean-Philippe Diguet, Kevin Martin and Daniel Sepulveda.

12:40    13:00 Closing Session


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