Call for Papers for Special Sessions

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DASIP 2014

Conference on Design & Architectures for Signal & Image Processing

October 8-10, 2014
Madrid, Spain



 

The Conference on Design & Architectures for Signal & Image Processing - DASIP provides an inspiring international forum for latest innovations and developments in the field of leading edge embedded signal processing systems. The conference features Special Sessions with the purpose of introducing the DASIP community to relevant hot topics that were not covered by previous editions of the conference.

Arithmetic for Image and Signal Processing
Co-Chairs:
Daniel Menard, UEB/INSA Rennes/IETR, FR
Gabriel Caffarena, Universidad CEU San Pablo, Madrid, ES

Just-in-Time Compilation and Mapping of Signal and Image Processing Computations to Reconfigurable Hardware
Co-Chairs:
Christian Plessl, University of Paderborn, DE
João M.P. Cardoso, University of Porto, PT
Michael Hübner, Ruhr-Universität Bochum, DE

Visual Scene Analysis on Hybrid Multicore
Co-Chairs:
Walter Stechele, Technical University of Munich, DE
Lionel Lacassagne and Michèle Gouiffès, University Paris Sud, FR
Martin Danek, daiteq, CZ

All submitted papers should be done online, following the paper submission guidelines. During paper submission, please take care to select the special session corresponding to your choice.

IMPORTANT DATES

Paper submission: April 21 May 5 May 19, 2014 (extended)
Notification of acceptance: July 14, 2014
Demo Night paper submission: June 16, 2014
Tutorial Proposals June 16, 2014
Camera ready papers: September 8, 2014

SUBMISSION REQUIREMENTS
Authors should submit their full papers (up to 8 pages, double-column IEEE format) in PDF through the web based submission system. Proceedings of DASIP 2014 will be submitted for inclusion into IEEE Xplore. Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in third person.

Full submission requirements, templates and submission instructions can be found at: http://www.ecsi.org/dasip/submissions

PUBLICATIONS
Each submission will receive at least three independent double blind reviews from the members of our scientific committee. Authors of accepted papers must address those comments in the camera ready version and present it in the conference prior to its publication. The conference proceedings will be published in electronic form with an ISSN and ISBN number and made available on the ECSI website and submitted for inclusion in the IEEE Xplore Digital Library. Paper and keynote presentation slides and tutorial documents will be made available to ECSI members and conference attendees after the conference (subject to confidentiality issues). Authors of the best papers will be invited to submit an extended version of their work to the International Journal of Signal Processing Systems (IJSPS) and the International Journal of Real-Time Image Processing (IJRTIP).

 


 

Arithmetic for Image and Signal Processing
Co-Chairs:
Daniel Menard, UEB/INSA Rennes/IETR, FR
Gabriel Cafferana, Universidad CEU San Pablo, Madrid, ES

Abstract:
Image and signal processing applications involve the execution of numerous mathematical operations. In order to fulfill embedded system constraints, a good adequacy between application performance and used arithmetic is sought. The trade-off cost and accuracy enables the optimization of the final implementation. However, new methods and tools are needed to keep time-to-market within standard bounds. As a result, the automation of some key processes (e.g. fixed-point data coding, arithmetic operator design, etc) is a key element.

The aim of this session is to present recent advances in the domain of architecture and arithmetic for image and signal processing applications. Fields of interest for this session include, but not limited to:      

  • Quantization of complex systems
  • Data representation (fixed-point, floating-point, custom floating-point, block floating-point, logarithmic number system, residue number system)
  • Arithmetic operators, function evaluation.
  • Optimized data-path design
  • Methods and tools for fixed-point conversion
  • Dynamic range evaluation
  • Numerical accuracy evaluation

 

 

Just-in-Time Compilation and Mapping of Signal and Image Processing Computations to Reconfigurable Hardware
Co-Chairs:
Christian Plessl, University of Paderborn, DE
João M.P. Cardoso, University of Porto, PT
Michael Hübner, Ruhr-Universität Bochum, DE

Abstract:
Just-in-time (JIT) compilation has become one of the most widespread software technologies. It effectively contributes to portability and to optimizations based on runtime data and specific target computing architecture features. Its adoption in the context of Reconfigurable Computing is however an open issue. Although reconfigurable hardware offers the runtime reconfigurability and programmability needed by JIT compilation and mapping approaches, FPGAs and other reconfigurable hardware accelerators have so far been used predominantly with the configurations generated offline. Dynamic reconfiguration mainly used for switching between configurations and adapting specific hardware properties.

Generating highly specialized application-specific or possibly even instance-specific, accelerators during execution promises to bring extra benefits to Reconfigurable Computing. However, there is still a need for solutions that reduce the time overhead caused by the long runtimes of hardware synthesis, placement and routing. One possibility is to address reconfigurable hardware architectures that significantly diminish those runtimes without compromising the performance gains too much.

In this special session, we intend to discuss recent research efforts on JIT compilation and mapping techniques applied to reconfigurable accelerators. These efforts range from developing new design flows applying ideas from JIT compilation of software to JIT hardware synthesis, over techniques aiming at drastically reducing the time for placement and routing at runtime (e.g., by composing pre-synthesized and pre-routed building blocks) to new reconfigurable architectures that allow for very fast placement and routing. If successful, the combination of these approaches may lead to self-optimizing computing systems that automatically move computations from the main CPU to reconfigurable accelerators allowing arbitrary applications to profit from the performance and energy-efficiency benefits of reconfigurable hardware.

This special session intends to bring together researchers that study aspects of just-in-time compilation and mapping for Reconfigurable Hardware (e.g., FPGAs, CGRAs). We hope to have presentations of recent state-of-the-art approaches, exchange ideas, and to discuss efforts on building common research platforms (tools, architectures, prototypes).

Topics
The topics of the special session include the JIT compilation and mapping aspects regarding the following subjects and mainly targeting signal and image processing computations:

  • Compilation and Optimizations
  • Intermediate Representations
  • Optimizations focused on Runtime Knowledge
  • Reconfigurable Hardware Architectures
  • Virtual Machines for Reconfigurable Hardware
  • FPGA Overlay Architectures for Fast Mapping of Hardware Accelerators
  • Placement and Routing
  • Hardware Support for JIT Compilation and Mapping
  • Monitoring
  • Hardware/Software Partitioning
  • Tools, Prototypes, Simulators
  • Power, Energy, and Performance Studies
  • Studies Showing Higher Impact Due to JIT Compilation and Mapping
 

 

Visual Scene Analysis on Hybrid Multicore
Co-Chairs:
Walter Stechele, Technical University of Munich, DE
Lionel Lacassagne and Michèle Gouiffès, University Paris Sud, FR
Martin Danek, daiteq, CZ

Abstract:
Visual scene analysis is gaining interest in many applications, including surveillance, robotics, and driver assistance. Major challenges include real-time techniques for visual scene analysis, on various levels of abstraction, from image data to higher level feature analysis. The focus of this year’s special session will be on optimization techniques for software and hardware parallel architectures, like RISC and hybrid manycore processors, hardware accelerators, GPU, and massively parallel processor arrays. Proposals for new programming methods and architectural extensions are welcome, as well as evaluation of benchmarking and comparison with respect to power, performance, and robustness.

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