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DASIP 2013

Conference on Design & Architectures for Signal & Image Processing

October 8-10, 2013
Cagliari, Italy


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DASIP 2013 Program
Click on the link in the table for the session description.

Tuesday, October 8

08:00-08:45 Registration & Coffee
08:45-09:00 Welcome
09:00-10:00 Keynote 1: Roberto Sarmiento, ULPGC
10:00-11:30 Session 1: Vision and Image Processing Architectures
11:30-12:00 Coffee Break
12:00-13:30 Session 2: Tools for DSP Algorithm Implementation
13:30-15:00 Lunch
15:00-16:30 Session 3 (SS): Visual Scene Analysis in 2D and 3D
16:30-17:00 Coffee Break
17:00-18:00 Session 4 (SS): Modern Localisation Techniques
19:00-21:30 Demo Night

 

Wednesday, October 9

08:30-09:00 Registration & Coffee
09:00-10:00 Keynote 2: Benoit Dupont de Dinechin, Kalray
10:00-11:30 Session 5: Image Processing Applications and Systems
11:30-12:00 Coffee Break
12:00-13:30 Session 6: Smart and Adaptive Devices
13:30-15:00  Lunch
15:00-15:45 Session 7 (SS): Advanced Image Processing for Space Applications
15:45-16:15 Coffee Break
16:15-17:30 Poster Introductions
19:00-21:30 Social Event & Poster Presentations

 

Thursday, October 10

08:30-09:00 Welcome Coffee
09:00-10:00 Keynote 3: Ioannis Sourdis, Chalmers University of Technology
10:00-11:00 Session 8: 3D Vision Systems and Applications
11:00-11:30 Coffee Break
11:30-12:30 Session 9 (SS): Software Defined Radio
12:30-12:45 Closing Session
12:45-13:45 Lunch
14:00-17:00 Cagliari Tour

 

Tuesday, October 8

08:00-08:45

Registration & Coffee

 

08:45-09:00

Welcome to DASIP

General Co-Chairs:
Paolo Meloni,
University of Cagliari

Christophe Jégo,
University of Bordeaux

 

09:00-10:00



Keynote 1
: Roberto Sarmiento,
University of Las Palmas de Gran Canaria (ULPGC), Institute for Applied Microelectronics (IUMA)

Towards real-time hyperspectral image processing and compression

Chair: Eduardo de la Torre, Universidad Politécnica de Madrid

Abstract:
Remotely sensed hyperspectral images are conformed by capturing the energy reflected or emitted by targets in a very high number of wavelengths, resulting in data cubes (hypercubes) that contain hundreds or even thousands of nearly contiguous spectral bands. Thanks to this sampling strategy, hyperspectral imaging systems provides much more information about the sensed scene than solutions based on panchromatic or multispectral approaches, which has favoured the exploitation of hyperspectral data for many applications. This fact has motivated the development of new hyperspectral sensors with increased spatial, spectral and even temporal resolutions, which produce formidable amounts of data to be transmitted, stored, and processed. For the case of applications under real-time or near real-time constraints, this demands fast processing solutions that can be used to compress and/or interpret hyperspectral data, performing a more efficient exploitation of hyperspectral data sets. For this purpose, Field Programmable Gate Array (FPGA) devices have demonstrated to offer an excellent compromise between flexibility, performance and power efficiency

This talk will review the fundamentals of hyperspectral imaging, focusing on the unmixing of hyperspectral images, which is the most popular technique for analysing the sub-pixel content of a given hyperspectral image, and on the efficient compression of these images. Moreover, FPGA-based case studies will be introduced, such as an endmember extraction FPGA-based architecture to be used as part of a hyperspectral linear unmixing processing chain, and the FPGA implementation of the hyperspectral imaging lossless compression standard recently uncovered by the Consultative Committee for Space Data System (CCSDS), namely the CCSDS123 standard.  Future challenges and directions within this research area will be also highlighted and discussed.

Bio:
Roberto Sarmiento is a Full-Professor at the Telecommunication Engineering Faculty at the University of Las Palmas de Gran Canaria, Spain, in the area of Electronic Engineering. He contributed to the birth of this centre in 1989. He was the Dean of the Faculty from 1994 to 1998 and Vice-Chancellor for Academic Affairs and Staff at the ULPGC from 1998 to 2003. In 1993, he was a Visiting Professor at the University of Adelaida, South Australia, and later at the University of Edith Cowan, also in Australia. He is a cofounder of the Institute for Applied Microelectronics (IUMA) and Director of the Integrated Systems Design Division of this Institute. Since 1990 he has published more than 40 journal papers and book chapters and more than 120 conference papers. Roberto Sarmiento has been awarded with four six years research periods by the National Agency for the Research Activity Evaluation in Spain. He has participated in more than 35 projects and research programmes funded by public and private organizations, from which he has been leader researcher in 16 of them. He has conducted several agreements with companies for the design of high performance integrated circuits, being the most remarkable the collaboration with Vitesse Semiconductor Corporation, California and Thales Alenia Space, Spain. His research interests include multimedia processing and video coding standard systems, reconfigurable architectures and real-time processing and compression of hyperspectral imaging.

 

10:00-11:30

Session 1: Vision and Image Processing Architectures

Chair: Bertrand Granado, UPMC LIP6

Abstract:
In this session there is 4 papers, the first one propose a new graphic processor with configurability in the rendering pipeline. Authors model this pipeline as a functional program and then manipulate a stream of tokens that can be iteratively modified. This new architecture enables dynamic thread creation and have a light-weight scheduling based on pattern matching.

The second article present a bio-inspired architecture based on Self-Organizing-Map proposed by Kohonen. The proposed architecture could increase the plasticity inside a many-core architecture. Author describe a hardware controller for a set of neuro-cognitive processes to drive a robot. The new bio-inspired architecture could be used to take allocation decision locally by taking into account emergent behavior of the network.

The third article present a multi-standard video architecture for the computation of DCT operation in H.264/AVC and HEVC. This architecture in totally configurable and scalable. It can compute all the transformation defined un H.264/AVC but also in HEVC coder. A FPGA implementation has been realized and shows an acceleration by at least 1.8 times, that allows UHDTV.

The last article present a template of heterogeneous shared memory cluster to help the realisation of tightly-coupled shared memory cluster of hardware accelerators for image and signal processing applications. This method help to obtain 40 % better performance than a simply larger main interconnect. In addition, authors propose a programming model to simplify applications developments.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

Tiago Dias (ISEL-PI Lisbon/INESC-ID/IST), Nuno Roma,
and Leonel Sousa (IST/INESC-ID)

Architecture and Programming Model Support for Efficient Heterogeneous Computing on Tigthly-Coupled Shared-Memory Clusters

Paolo Burgio, Andrea Marongiu (University of Bologna),
Robin Danilo, Philippe Coussy
(Université de Bretagne Sud/Lab-STICC),
Luca Benini (University of Bologna)

A Neural Model for Hardware Plasticity in Artificial Vision Systems

Laurent Rodriguez, Laurent Fiack, and Benoît Miramond
(ETIS UMR8051 CNRS/ENSEA/UCP)

A Novel Graphics Processor Architecture Based on Partial Stream Rewriting

Lars Middendorf and Christian Haubelt
(University of Rostock)

 

11:30-12:00

Coffee Break

 

12:00-13:30

Session 2: Tools for DSP Algorithm Implementation

Chair: Francesca Palumbo, University of Cagliari

Abstract:
Modern parallel and heterogeneous architectures require fulfilling a diverse and wide set of requirements, accordingly to the market scenarios they are tailored for. This may imply to conceive new and more efficient design methodologies capable to early stage management of complexity, flexibility and computing efficiency as well as power balancing.

All the paper presented in this Section deal with the notion of level design, specifically focusing on high-level modeling and simulation. The first two papers address design space exploration issues for complex and heterogeneous systems modeled using high level dataflow representations. The third paper copes with early stage energy consumption estimations leveraging as well on the same kind of system representations. Finally, the last paper is specifically related to dataflow modeling advances, presenting a method based on control tokens to derive more efficient actors’ schedulers.

TURNUS: a Unified Dataflow Design Space Exploration Framework for Heterogeneous Parallel Systems

Simone Casale-Brunet, Claudio Alberti,
Marco Mattavelli (EPFL),
and Jorn W Janneck (Lund University)

System-Level PMC-driven Energy Estimation Models in RVC-CAL Video Codec Specifications

Rong Ren, Eduardo Juarez Martinez, Cesar Sanz Alvaro
(Universidad Politecnica de Madrid),
Mickaël Raulet (IETR/INSA Rennes),
Fernando Pescador Del Oso
(Universidad Politecnica de Madrid)

Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study

Ab Al-Hadi Ab Rahman, Simone Casale Brunet,
Claudio Alberti, and Marco Mattavelli (EPFL)

Modeling Control Tokens for Composition of CAL Actors

Johan Ersfolk (Åbo Akademi University),
Ghislain Roquier (EPFL),
Johan Lilius (Åbo Akademi University),
and Marco Mattavelli (EPFL)

 

13:30-15:00

Lunch

 

15:00-16:30

Session 3 (Special Session): Visual Scene Analysis in 2D and 3D

Chair: Marek Gorgon, AGH University of Science and Technology
Co-Chair: Lionel Lacassagne, University Paris Sud

Abstract:
Due to the evolution of digital cameras, visual scene analysis is gaining interest in many applications. In this special session, the focus will be on real-time techniques for visual scene analysis, including surveillance, robotics, and driver assistance, for both 2D and 3D algorithms, on various levels of abstraction, from image data to higher level feature analysis. Hardware/software optimization techniques for many-core processors with NoC, FPGA, GPU, DSP will be included, with a focus on co-optimization for both hardware and software.

A Resource-Aware Nearest Neighbor Search Algorithm for K-Dimensional Trees

Johny Paul, Walter Stechele, Manfred Kröhnert,
and Tamim Asfour (Karlsruhe Institute of Technology),
Benjamin Oechslein, Christoph Erhardt, Jens Schedel,
Daniel Lohmann, and Wolfgang Schröder-Preikschat
(University of Erlangen-Nuremberg)

Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays

Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig,
and Jürgen Teich (University of Erlangen-Nuremberg)

Real-Time RGB-D Data Processing on GPU Architecture

Massimo Camplani, Antonio Blasco, Daniel Berjón,
Luis Salgado, and Francisco Morán
(Universidad Autonoma de Madrid)

Real-Time Covariance Tracking Algorithm for Embedded Systems

Andrés Romero Mier Y Teran, Lionel Lacassagne
(Laboratoire de Recherche en Informatique),
Ali Hassan Zahraee (Institut d’Electronique Fondamentale),
and Michèle Gouiffès (Laboratoire d’Informatique pour la Mécanique)

 

16:30-17:00

Coffee Break

 

17:00-18:00

Session 4 (Special Session): Modern Localisation Techniques

Chair: Jari Nurmi, Tampere University of Technology

Abstract:
There is a high demand for providing robust and accurate localization solutions, which will be available continuously, regardless of the specific environment, i.e., outdoors and indoors, and which would overcome and complement the drawbacks of the current stand-alone single-frequency satellite-based navigation systems. In this session the authors are addressing innovative signal processing methods and their implementations, in order to improve the state-of-the art in localization. In particular the papers deal with modeling of inertial sensors based on Micro-Electromechanical Systems (MEMS) for localization purposes, detection of multipath propagation, which often represents the dominant error source in GNSS (Global Navigation Satellite Systems) positioning, and a linear state model for positioning combining PDR (Pedestrian Dead Reckoning) and WLAN signals.

A Linear State Model for PDR+WLAN Positioning

Matti Raitoharju, Henri Nurminen, and Robert Piché
(Tampere University of Technology)

Constrained Non-linear Fitting for Stochastic Modeling of Inertial Sensors

Alex Garcia Quinchia (Universitat Autònoma de Barcelona),
Gianluca, Fabio Dovis
(Politecnico di Torino and Istituto Superiore Mario Boella),
and Carles Ferrer (Universitat Autònoma de Barcelona)

Effects of Colored Noise in Linear Adaptive Filters Applied to GNSS Multipath Detection

Sabrina Ugazio (Istituto Superiore Mario Boella)
and Letizia Lo Presti (Politecnico di Torino)

 

19:00-21:30

Demo Night

Co-Chairs:
Francesca Palumbo, University of Cagliari, Italy
Gabriel Marchesan Almeida

During the DASIP 2013 Demo Night, universities and public research institutes are invited to demonstrate their hardware platforms, prototypes and tools. Demos shown at the Demo Night are accompanied by a short paper describing the demo and associated work, which are included in the conference Proceedings.

The goal of this event is to present collaborative projects and to show demonstrations. DASIP Demo Night includes a reception with a casual social environment conducive to friendly discussions and networking.

The Demo Night is included in the conference registration fee. Possibility to register for the Demo Night separately.

Conference venue
The Ghetto - Cultural Center
Via Santa Croce, 18
09100 Cagliari
Phone: 070 6670190

Demonstrations

Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework

Simone Casale Brunet, Endri Bezati, Claudio Alberti,
Ghislain Roquier, Marco Mattavelli (EPFL),
Jorn W Janneck (Lund University),
and Jani Boutellier (University of Oulu)

Dynamic Source Code Analysis for Memory Hierarchy Optimization in Multimedia Applications

Christakis Lezos, Grigoris Dimitroulakos
(University of Peloponnese),
Angeliki Freskou (Ajax Compilers),
and Konstantinos Masselos (University of Peloponnese)

Evaluation of Driver Assistance Systems with a Car Simulator using a Virtual and a Real FPGA Platform

Philipp Wehner and Diana Goehringer
(Ruhr-University Bochum)

Framework for Fast Prototyping of Applications Running on Reconfigurable System on Chip

Jan Viktorin, Pavol Korcek, Vlastimil Kosar and Jan Korenek
(Brno University of Technology)

Networked Embedded Acoustic Processing System for Smart Building Applications

Sebastian Uziel, Thomas Elste, Wolfram Kattanek (IMMS),
Danilo Hollosi, Stephan Gerlach, and Stefan Goetze (IDMT)

A Noise-Agnostic Self-Adaptive Image Processing Application Based on Evolvable Hardware

Javier Mora, Ángel Gallego, Andrés Otero,
Eduardo de La Torre and Teresa Riesgo
(Universidad Politécnica de Madrid)

A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture

Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig,
and Jürgen Teich (University of Erlangen-Nuremberg)

Prototype of a novel Steady-State Load Identification Technique for Digitally Controlled DC-DC Power Supplies

Andrea Congiu, Massimo Barbaro, Andrea Picciau
(University of Cagliari),
 Emanuele Bodano, and Dirk Hammerschmidt
(Infineon Technologies)

Spatial Edge Directed Video Deinterlacing

Prateek Murgai (Delhi Technological University)
and Maria Trocan (Institut Superieur d'Electronique de Paris)

 

Wednesday, October 9

08:30-09:00

Registration & Coffee

 

09:00-10:00



Keynote 2:
Benoît Dupont de Dinechin, Kalray

Latency-Constrained Image and Signal Processing on a Manycore Processor

Chair: Christophe Jego, Institut Polytechnique de Bordeaux

Abstract:
Image and signal processing in embedded applications are often constrained by the end-to-end latency. Classic platforms that support these applications rely on FPGA or farms of digital signal processors that run under the supervision of micro-controllers. There are significant advantages to hosting those applications on manycore platforms, in particular reducing the system size, weight, and power (SWaP), while improving programmability. However, existing manycore platforms based on CPU or GPU and the associated software stacks do not allow for predictable or even repeatable processing latencies.

We present the architecture and programming models of the MPPA-256 processor, which integrates 256 processing engine (PE) cores and 32 resource management (RM) VLIW cores on a single 28nm CMOS chip. We discuss how this processor and its programming models are especially suited to compute-intensive image and signal processing applications under latency constrains. We also introduce the metalibm library generator for the Kalray VLIW cores, which automatically produces high-performance and correctly rounded implementations for application-specific specializations of the C99 libm and IEEE 754-2008 mathematical functions.

Bio:
Benoît Dupont de Dinechin is Chief Technology Officer of Kalray (http://www.kalray.eu), a company that manufactures integrated manycore processors for embedded and industrial applications. He is also the Kalray VLIW core main architect, and co-architect of the Kalray Multi Purpose Processing Array (MPPA). Before joining Kalray, Benoît was in charge of Research and Development of the STMicroelectronics Software, Tools, Services division, with special focus on compiler design, virtual machines for embedded systems, and component-based software development frameworks. He was promoted to STMicroelectronics National Fellow in 2008. Prior to his work at STMicroelectronics, Benoît worked part-time at the Cray Research park (Minnesota, USA), where he developed the software pipeliner of the Cray T3D production compilers. Benoît earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Supérieure de l'Aéronautique et de l'Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill university (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao.

 

10:00-11:30

Session 5: Image Processing Applications and Systems

Chair: Sebastian Lopez, University of Las Palmas de Gran Canaria

SiPM Based Smart Pixel for Photon Counting Integrated Streak Camera

Imane Malass, Wilfried Uhring, Jean-Pierre Le Normand,
Norbert Dumas, Virginie Zint, and Foudil Dadouche
(University of Strasbourg and CNRS)

A Coarse-Grained Reconfigurable Wavelet Denoiser exploiting the Multi-Dataflow Composer tool

Nicola Carta, Carlo Sau, Francesca Palumbo,
Danilo Pani, and Luigi Raffo (University of Cagliari)

A Runtime Adaptive H.264 Video-Decoding MPSoC Platform

Giuseppe Tuveri, Simone Secchi, Paolo Meloni
(DIEE, University of Cagliari),
Emanuele Cannella (LIACS, Leiden University),
and Luigi Raffo (DIEE, University of Cagliari)

Foreground Object Features Extraction with GLCM Texture Descriptor in FPGA

Mateusz Komorkiewicz and Marek Gorgoń
(AGH University of Science and Technology)

 

11:30-12:00

Coffee Break

 

12:00-13:30

Session 6: Smart and Adaptive Devices

Chair: Benoît Miramond, ETIS

Abstract:
The evolution of technology still brings together new opportunities and challenges. Smart and adaptive devices get a different perspective on digital architecture design face to conventional computation paradigms. And that is precisely this different point of view that can bring solutions to today's design challenges.

In this session, ant colony heuristics are proposed to reduce complexity of architecture synthesis for large data-flow designs. In the application domain of medical and body-monitoring, a dedicated smart device shows the benefits of in-sensor processing in term of communication, consumption and performance. A new approach of evolvable hardware brings better adaptation in the context of adaptive image filtering. Finally, the on-line adaptation of embedded devices is studied in the context of fault-tolerance where a generalized architecture for quasi-cyclic LDPC codes is presented.

A Hierarchical Ant-Colony Heuristic for Architecture Synthesis for On-Chip Communication

Wei Tang and Forrest Brewer
(University of California, Santa Barbara)

Smart Sensor Architectures for Embedded Biosignal Analysis

Benjamin Pfundt, Marc Reichenbach, Björn Eskofier,
and Dietmar Fey (FAU Erlangen-Nürnberg)

Noise-agnostic Adaptive Image Filtering without Training References on an Evolvable Hardware Platform

Javier Mora, Ángel Gallego, Andrés Otero,
Eduardo de La Torre, and Teresa Riesgo
(Universidad Politécnica de Madrid)

FPGA Accelerator of Quasi Cyclic EG-LDPC Codes Decoder for NAND Flash Memories

Syed Azhar Ali Zaidi, Muhammad Awais, Carlo Condo,
Maurizio Martina, and Guido Masera (Politecnico di Torino)

 

13:30-15:00

Lunch

 

15:00-15:45

Session 7 (Special Session): Advanced Image Processing for Space Applications

Chair: Eduardo Juarez, Universidad Politecnica de Madrid

Abstract:
In the last years, all space agencies have increased their research efforts in order to enhance the success rate of their missions. Two research topics are currently very active to achieve this goal: active debris removal and guided landing. The former aims at finding new methods to remove space debris exploiting unmanned spacecrafts with high vision capabilities, i.e., the spacecraft must be able to take and process pictures with complex image processing algorithms in order to detect, track and analyze the debris. The latter concerns to the adoption of Video Based Navigation systems to assist the entry, descent and landing (EDL) phase of space modules enhancing the precision of automatic EDL navigation systems.

In both research domains, all algorithms must guarantee real-time performance. Because of the difficulties a software implementation of these computational intensive tasks finds to meet the hard deadlines, these algorithms must be accelerated via hardware. Moreover, this last aspect introduces new issues in terms of system reliability.

This Special Session focuses on new image processing algorithms and their implementations. The session will consists of two  talks, one from from the industry (EURIXGroup) and one from the academic experience (Politecnico di Torino).

Airport Markings Recognition for Automatic Taxiing

Federico Francesco and Walter Allasia (EURIXGroup)

Stereo Vision System for Capture and Removal of Space Debris

Francesco Rosso, Francesco Gallo, Walter Allasia,
and Enrico Licata (EurixGroup),
Paolo Prinetto, Daniele Rolfo, and Pascal Trotta
(Politecnico di Torino),
Alain Favetto, Marco Paleari, and Paolo Ariano
(Istituto Italiano di Tecnologia)

 

15:45-16:15

Coffee Break

 

16:15-17:30

Poster Introductions

A 3D reconstruction from real-time stereoscopic images using GPU

Jose Gomez-Balderas and Dominique Houzet (GIPSA-Lab)

Accelerating a Modified Gaussian Pyramid with a Customized Processor

Diana Gil, Pierre Langlois, and Yvon Savaria
(Ecole Polytechnique de Montreal)

Communication Cost Reduction for Hardware Tasks Placed on Homogeneous Reconfigurable Resource

Quang-Hai Khuat and Daniel Chillet
(University of Rennes 1, IRISA/INRIA)

Design and Analysis of an FPGA based Encoder SoC for Locally Stationary Image Source

Yuhui Bai, Syed Zahid (ETIS - ENSEA),
and Bertrand Granado (LIP6)

Efficient Bit Decoding Implementation for Mass Market Multi-Constellation GNSS Receivers

Tommi Paakki, Jussi Raasakka, Francescantonio Della Rosa,
and Jari Nurmi (Tampere University of Technology)

Embedded Vision-based SLAM: A Model-driven Approach

Jonathan Piat (LAAS/CNRS), David Marquez (LAAS-CNRS),
and Michel Devy (LAAS)

Evaluation of an RTOS on top of a Hosted Virtual Machine System

Mehdi Aichouch, Jean-Christophe Prévotet,
and Fabienne Nouvel (IETR laboratory INSA-Rennes)

Exploring Frequency Tuning Policies for USRP-N210 SDR Platform and GNU Radio

Islam Galal and Mostafa Ibrahim (Benha University)

Memory Access Analysis and Optimization of a Parallel H.264/SVC Decoder for an Embedded Multi-Core Platform

Jens Brandenburg and Benno Stabernack
(Fraunhofer Heinrich Hertz Institute)

A Novel Inter-Layer Intra Prediction Architecture for Real-Time SVC Video Codecs

Yeray Hernandez, Sebastian Lopez, Gustavo Callico,
Jose Lopez, and Roberto Sarmiento
(University of Las Palmas de Gran Canaria)

Particle Filters and Resampling Techniques: Importance in Computational Complexity Analysis

Biruk Getachew Sileshi
(Universitat Autònoma de Barcelona),
Carles Ferrer (Institut de Microelectrònica de Barcelona),
and Joan Oliver (Universitat Autònoma de Barcelona)

Task Migration of DSP Application Specified with a DFG and Implemented with the BSP Computing Model on a CPU-GPU Cluster

Farouk Mansouri, Sylvain Huet, Vincent Fristo,
and Dominique Houzet (GIPSA-lab)

Tetrahedral Volume Reconstruction in X-Ray Tomography using GPU Architecture

Michele A. Quinto (CEA),
Dominique Houzet (GIPSA-lab, Grenoble-INP),
and Fanny Buyens (CEA)

 

19:00-21:30

Social Event & Poster Presentations

This year banquet will be held, together with a poster session, in the beautiful de Candia palace. Located in the medieval quarter of Castello and overlooking the city and its gulf, an historical residence built in 1850 by Mario De Candia, a great tenor acclaimed in European theatres and courts and in memorable matinees with Chopin. It has great ambience for hosting social events and dinners, providing different indoor and outdoor experiences to create a perfect atmosphere for any event.

The DASIP 2013 Poster Session will be hosted in the panoramic terrace, before the Banquet.

Visit the Social Event page for more information.

 

Thursday, October 10

08:30-09:00

Welcome Coffee

09:00-10:00



Keynote 3: Ioannis Sourdis, Chalmers University of Technology

Challenges in the design of future SoCs and the role of Reconfigurable Computing

Chair: Sébastien Pillement, Polytech University of Nantes

Abstract:
The new developments in semiconductor technology cause significant problems in SoC performance, power consumption and reliability, indicating that the “golden” CMOS era is long gone. Technology scaling does not deliver any longer significant performance speedup, the increasing power density poses severe limitations in chips, while, transistors become less reliable. In the face of such changes in the technological landscape, the design of future SoCs is becoming more challenging. New, more efficient design techniques are needed to improve power efficiency, to increase SoC performance and functionality as well as to provide fault-tolerance at lower (power, energy and performance) costs. This talk will first address the above challenges and suggest future directions for the design of more efficient, adaptive SoCs using reconfigurable hardware. The second part of the talk focuses on the design of future fault-tolerant SoCs, describing the concepts of the DeSyRe FP7 European project (DeSyRe: on-Demand System Reliability – www.desyre.eu). The DeSyRe SoC architecture exploits a flexible reconfigurable hardware substrate coupled with runtime system optimization and management techniques to build a SoC, which is on-demand adaptive to the various fault-types and fault rates as well as to the application requirements and system constraints.

Bio:
Ioannis Sourdis is an Assistant Professor in Computer Engineering at Chalmers University of Technology, Sweden. He has an engineering diploma Dipl-Eng ('02) and a MSc ('04) in electronic and computer engineering from the TU Crete, Greece, and a PhD ('07) in computer engineering from TU Delft, The Netherlands. His research interests include architecture and design of computer and networking systems, reconfigurable computing, interconnection networks and multiprocessor parallel systems, fault-tolerant computing and energy-aware computing. From 2007 until 2010, Sourdis participated in the coordination of the HiPEAC NoE cluster on Reconfigurable Computing. He has co-authored about 30 papers in Int. conferences and journals, cited in over 700 papers. He is participating in the technical committees of 14 Int. conferences; he is reviewer in 21 Int. journals and more than 30 Int. conferences. Sourdis holds a patent in an address lookup technique for network routing. He participated in the Pro3, EASY, SARC and HiPEAC European projects, and since 2011 he coordinates the DeSyRe FP7 project. He is also member of the HiPEAC NoE, member of the management committee of the MEDIAN Cost Action, member of IEEE and ACM.

 

10:00-11:00

Session 8: 3D Vision Systems and Applications

Chair: Wilfried Uhring, University of Strasbourg and CNRS

Abstract:
Nowadays, 3D vision is a common tool that is now available in the consumer electronics and many current and future applications require high speed estimation of the object depths of acquired image scenes. High speed acquisition and image processing are challenging tasks that are the heart of this session. According to the process and acquisition requirement, the best hardware architectures have to be found.

The first paper presented in this section deal with and hardware implementation of the generalized Hough Transform for Stereo Correspondence on a FPGA. The processing speed exceeds 500 frames per second with high resolution.

The second paper presents two original architectures of high speed imager that take advantage of the 3D stacking microelectronic technology that makes a massively parallel processing possible . The proposed architectures are able to handle 1,25Tpixel per second with unmatched memory depth of 900 frames.

The third paper reports a real-time GPU-based stereo matching algorithm. The algorithm has been implemented on a GPU platform using a high level compiler HMPP which greatly reduces the development time and makes use of the parallel computing of GPU device with CUDA. The GPU-based implementation of the proposed method obtains 20 fps.

Real-Time GPU-based Local Stereo Matching Method

Jinglin Zhang, Jean-Francois Nezan,
and Jean-Gabriel Cousin (INSA-Rennes)

New 3D-Integrated Burst Image Sensor Architectures with in-situ A/D conversion

Rémi Bonnard, Fabrice Guellec, Josep Segura Puchades,
Antoine Dupret (CEA LETI/DACLE/L3I),
and Wilfried Uhring (CNRS ICube/DESSP/SMH)

Extension and FPGA Architecture of the Generalized Hough Transform for Real-Time Stereo Correspondence

Frank Schumacher and Thomas Greiner
(Pforzheim University)

 

11:00-11:30

Coffee Break

 

11:30-12:30

Session 9 (Special Session): Software Defined Radio

Chair: Julien Lekernec, University of Nottimgham, Ningbo, CN
Co-Chair: Olivier Romain, Laboratoire ETIS - UMR8051 - ENSEA - UCP, FR

Abstract:
Software defined radio represents an exciting research area worldwide and could become one of the key technology of the 21st systems, improved ADC sampling rates and DSP clock speeds are pushing digital signal processors progressively closer to the antenna, allowing tasks previously performed in fixed analog hardware or a workstation to be carried out on programmable or reconfigurable processors – the so- called Software Defined Radio (SDR) approach. While much of the initial interest in SDR was focused on personal communications systems, there has been growing interest in extending the advantages of SDR in many applications domains such as broadcasting (radio and TV), radar systems, green communication, vehicular communication, dynamic spectrum sensing, dirty RF, etc. Moreover, embedding intelligence into SDR systems opens up the space to design efficient radio communications to suit a specific need and to develop systems that can adapt based on local resources and electromagnetic environment to perform its task.

Today, this special session will discuss recent advances in Software Defined Radio, including processing architecture with the An Efficient GPU Implementation of an Arbitrary Resampling Polyphase Channelizer that will be presented by the University of the Maryland. This first presentation will be followed by an article that deals with a low-cost ring interconnect as a bus replacement for small to medium scale real-time multiprocessor systems. This paper will be presented by the University of Twente. Finally, the University of Technology of Tampere will present a paper on the design and evaluation of two algorithms for the implementation of a matched filter for timing synchronization in receiver architectures.

An Efficient GPU Implementation of an Arbitrary Resampling Polyphase Channelizer

Scott Kim, William Plishker, Shuvra Bhattacharyya
(University of Maryland)

Low-Cost Guaranteed-Throughput Communication Ring for Real-Time Streaming MPSoCs

Berend Dekens, Marco Bekooij, Philip Wilmanns,
and Gerard Smit (University of Twente)

Design of a Matched Filter for Timing Synchronization

Roberto Airoldi and Jari Nurmi
(Tampere University of Technology)

 

12:30-12:45

Closing Session

 

12:45-13:45

Lunch

 

14:00-17:00

Cagliari Tour
Sponsored by the University of Cagliari

Visit the Social Event page for more information.

 


DASIP 2013 is organized with the technical co-sponsorship of
the IEEE Signal Processing Society

    


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