Call for Contributions for Special Sessions

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DASIP 2012

Conference on Design & Architectures for Signal & Image Processing

October 23-25, 2012
Karlsruhe, Germany

 

DASIP 2012 will feature five Special Sessions with the purpose of introducing the DASIP community to relevant hot topics that were not covered by previous editions of the conference.

Architectures for Forward Error Correction Decoders
Co-Chairs:
Matthieu Arzel, Telecom Bretagne, FR
Camille Leroux, Enseirb-Matmeca, FR

Arithmetic for Image and Signal Processing
Co-Chairs:
Gabriel Caffarena, U. CEU San Pablo, ES
Daniel Menard, U. of Rennes 1, FR

Methods and Tools Based on Dataflow Models
Co-Chairs:
Johan Lilius, Abo University, FI
Jean François Nezan, INSA Rennes, FR

Reconfigurable Systems and Tools for Signal and Image Processing
Co-Chairs:
Diana Göhringer, Fraunhofer IOSB, DE
Juanjo Noguera, Xilinx, IE
Sebastien Pillement, U. of Rennes 1, FR

Visual Surveillance
Co-Chairs:
Marek Gorgon, U. of AGH, PL
Walter Stechele, TUM, DE

 

All submitted papers should be done online, following the paper submission guidelines. During paper submission, please take care to select the special session corresponding to your choice.

Please provide the following information in a special session proposal:

  • Title of the special session proposed
  • Name(s) and affiliation(s) of the chair(s)
  • Keywords
  • Abstract (700 characters)
  • Information about expected papers (number, affiliation of authors ...)
  • Information about potential reviewers

IMPORTANT DATES
Paper submission deadline: April 30, 2012 May 14, 2012 (extended)
Notification of acceptance: June 25, 2012
Camera ready papers: September 17, 2012

SUBMISSION REQUIREMENTS
Authors should submit their full papers (up to 8 pages, double-column IEEE format) in PDF through the web based submission system. Proceedings of DASIP 2012 will be included in the IEEE Xplore Digital Library. Submitted papers should be anonymous, are required to describe original unpublished work and must not be under consideration for publication elsewhere. After the conference, papers and presentations will be published on the ECSI website together with the keynote presentations (subject to confidentiality issues). Authors of the best papers will be invited to submit an extended version of their work to the International Journal of Real-Time Image Processing (IJRTIP), in which a special issue on DASIP will be published in the third quarter of 2012. The selected best papers from several DASIP editions will be published in a book edited by SPRINGER.

ORGANIZING COMMITTEE
General Co-Chairs:

Michael Hübner, Ruhr-Universität Bochum, Germany
Daniel Chillet, Université de Rennes 1, France

Program Co-Chairs:
Paolo Meloni, University of Cagliari, Italy
Christophe Jego, Bordeaux Institute of Technology, France

Local Coordinators:

Gabriel Marchesan Almeida, Karlsruhe Institute of Technology, Germany
Diana Göhringer, Karlsruhe Institute of Technology, Germany

Technical Program Committee
Mohamed Abid, CES laboratory, National School of engineers of Sfax (ENIS), TN
Tapani Ahonen, Tampere University of Technology, FI
Thugrul Arslan, University of Edinburgh, GB
Matthieu Arzel, Telecom Bretagne, FR
Jean Philippe Babau, University of Occidental Britanny - LISYC, FR
Iuliana Bacivarov, ETH Zurich, CH
Shailendra Baraniya, NMIMS University, IN
Cecile Belleudy, University of Nice-Sophia Antipolis/Laboratory LEAT, FR
Rabie Ben Atitallah, UVHC/LAMIH, FR
Mladen Berekovic, IMEC, NL
Christophe Bobda, University of Arkansas, US
Jalil Boukhobza, University of Occidental Britanny, FR
Ahmed Bouridane, Northumbria University Newcastle, GB
Jani Boutellier, University of Oulu, FI
Giovanni Busonera, CRS4, IT
Joan Cabestany, Universitat Politècnica Catalunya UPC, ES
Gabriel Caffarena, University CEU San Pablo, ES
João Cardoso, University of Porto, FEUP, PT
Emmanuel Casseau, IRISA/INRIA, FR
Stéphane Chevobbe, CEA LIST, FR
Daniel Chillet, IRISA, FR
Christopher Claus, Telemotive AG, DE
Gwenolé Corre, CEA, FR
Milos Drutarovsky, Technical University of Kosice, SK
Marc Duranton, CEA-LIST, FR
Ahmet Erdogan, University of Edinburgh, GB
Carles Ferrer, IMB-CNM (CSIC) & UAB, ES
Alberto Garcia-Ortiz, Univerisity of Bremen / ITEM, DE
Patrick Garda, University Pierre and Marie Curie, FR
Guy Gogniat, Université de Bretagne Sud, FR
Diana Göhringer, Karlsruhe Institute of Technology, DE
Marek Gorgon, AGH University of Science and Technology, PL
Bertrand Granado, ETIS/ENSEA/CNRS/UCP, FR
Arnaud Grasset, Thales Research & Technology, FR
Frank Hannig, University of Erlangen-Nuremberg, DE
Dominique Houzet, GIPSA-Lab, FR
Gareth Howells, University of Kent, UK
Michael Hübner, Ruhr-Universität Bochum, DE
Jorn Janneck, Lund University, SE
Christophe Jego, Institut Polytechnique de Bordeaux FR
Nathalie Julien, Lab-STICC Lorient FR
Udo Kebschull, University of Frankfurt, DE
Peter Koch, Aalborg University, Center for Software Defined Radio, DK
Ouassila Labbani-Narsis, LE2I, FR
Vianney, Lapôtre, Université de Bretagne-Sud, FR
Johann Laurent, Lab-STICC, FR
Yannick Le Moullec, Aalborg University, DK
Jean-Didier Legat, Université catholique de Louvain BE
Camille Leroux, Enseirb-Matmeca, FR
Shujun Li, University of Konstanz, DE
Johan Lilius, Abo University, FI
Yuzhe Liu, University of Notre Dame, US
Stéphane Mancini, TIMA laboratory FR
Philippe Manet, Université Catholique de Louvain BE
Marco Mattavelli, EPFL, CH
Klaus McDonald-Maier, University of Essex, UK
Samy Meftali, Université de Lille 1 - INRIA FR
Paolo Meloni, University of Cagliari, IT
Daniel Menard, University of Rennes 1, FR
Dragomir Milojevic, Université Libre de Bruxelles, BE
Benoît Miramond, ETIS – UMR 8051 – ENSEA Cergy, FR
Adam Morawiec,  ECSI, FR
Jean François Nezan, INSA Rennes, IETR laboratory, FR
Smail Niar, University of Valenciennes/LAMIH, FR
Juanjo Noguera, Xilinx, IE
Tokunbo Ogunfunmi, Santa Clara University US
Michel Paindavoine, University of Burgundy - LE2I, FR
Vassilis Paliouras, University of Patras, GR
Francesca Palumbo, University of Cagliari/DIEE, IT
Danilo Pani, University of Cagliari/DIEE, IT
Sebastien Pillement, University of Rennes 1 - IRISA/INRIA, FR
Mickael Raulet, IETR/INSA Rennes, FR
Frederic Robert, Universite libre de Bruxelles, BE
Olivier Romain, ENSEA, FR
Gilles Sassatelli, LIRMM, University of Montpellier II / CNRS, FR
Simone Secchi, Pacific Northwest National Laboratory, US
Eric Senn, Université de Bretagne Sud, FR
Mohamed Shawky,  Heudiasyc/UTC, FR
Gilles Sicard, TIMA Laboratory, Joseph Fourier University of Grenoble, FR
Yves Sorel, INRIA Rocquencourt FR
Dimitrios Soudris, National Technical University of Athens, GR
Walter Stechele, Technical University of Munich, DE
Jarmo Takala, Tampere University of Technology, FI
Mathieu Thevenin, CEA-LIST, FR
Arnaud Tisserand, IRISA/CNRS - University of Rennes, FR
François Verdier, LEAT/University of Nice-Sophia Antipolis - UMR CNRS 6071, FR
Nikolaos Voros, Technological Educational Institute of Mesolonghi, GR
Serge Weber, University of Nancy, FR
John Williams, Petalogix, AU
Matthieu Wipliez, IETR/INSA University of Rennes, FR
Olivier Zendra, INRIA, FR

LOCAL ORGANIZER

Karlsruhe Institute of Technology, Germany

SECRETARIAT
ECSI Office
office [at] ecsi [dot] org
Ph: +33 4 76 63 49 34
Fax: +33 9 58 08 24 13


Architectures for Forward Error Correction Decoders
Co-Chairs:

Matthieu Arzel, Telecom Bretagne, FR
Camille Leroux, Enseirb-Matmeca, FR
Abstract:

In telecommunication systems, Forward Error Correction (FEC) is used to improve digital communication quality. Error correction encoding consists in the addition of redundancy to the binary information sequence before the transmission over a communication channel. This redundancy allows the FEC decoder to detect and/or to correct the effects of noise and interference encountered during the transmission of the information. Nowadays, more advanced FEC techniques such as Turbo codes or LDPC codes closely approach the ultimate limit of channel capacity on a variety of channel models. They are two families of FECs that are especially attractive for digital communication standards and have been adopted as part of several ones such as WiFi (IEEE802.11n), WiMax (IEEE802.16e), 10GBASE-T (IEEE 802.3an), UMTS (third mobile communication generation), 3GPP-LTE (the last step toward the fourth generation) or Digital Video Broadcasting (DVB-S2, T2 and C2). But, the design of multi-standard FEC decoder architecture is still a major challenge. Indeed, the lack of homogeneity in codes constructions leads to over dimensioned and/or partially compliant decoders. Since their success in wireless and wired communication systems, FEC codes are envisaged in very-constrained applications. For instance, innovative FEC codes and decoder architectures have to be proposed to cope with the needs of next-generation optical communications in lower error bounds and higher throughputs, of ultra-low power sensor systems, and of reliable nano-electronic devices.

Submissions of papers are invited in (but not only) any of the following topics, and in related areas:

  • Hardware Architectures
  • Design of architecture-aware FEC codes
  • Multi-standard FEC decoders
  • Low-power FEC decoders
  • High-throughput FEC decoders
  • FEC codes for reliable devices

Arithmetic for Image and Signal Processing
Co-Chairs:

Gabriel Cafferana, U. CEU San Pablo, ES
Daniel Menard, U. of Rennes 1, FR
Abstract:
Image and signal processing applications involve the execution of numerous mathematical operations. In order to fulfil embedded system constraints, a good adequacy between application performance and used arithmetic is sought. The trade-off between cost and accuracy enables the optimization of the final implementation. However, new methods and tools are needed to keep time-to-market within standard bounds. As a result, the automation of some key processes (e.g. fixed-point data coding, arithmetic operator design, etc) is a key element.

The aim of this session is to present recent advances in the domain of architecture and arithmetic for image and signal processing applications. Fields of interest for this session include, but not limited to:
  • Quantization of complex systems
  • Data representation (fixed-point, floating-point, custom floating-point, block floating-point, logarithmic number system, residue number system)
  • Arithmetic operators, function evaluation
  • Optimized data-path design
  • Methods and tools for fixed-point conversion
  • Dynamic range evaluation
  • Numerical accuracy evaluation
  • Multiple Word-Length High-Level Synthesis
  • Software implementation with sub-word parallelism or multi-precision.

Methods and Tools Based on Dataflow Models
Co-Chairs:

Johan Lilius, Abo University, FI
Jean François Nezan, INSA Rennes, FR
Abstract:
Dataflow models aim at describing a program as a directed graph of the data flowing (edges of the graph) between operations (nodes of the graph also called actors). The Models of Computation (MoC) associated with a dataflow graph govern the interaction between the actors. Dataflow models have been shown to provide efficient descriptions of algorithms for datadominated problem domains like video coding or radio algorithms. As an example in the video coding domain, RVC-CAL has been introduced as a standardised dataflow language for describing video codecs in the Reconfigurable Video Coding (RVC) standard. There is therefore a strong interest in developing methods and tools that will allow the efficient creation of implementations from such descriptions. The aim of this special session is to present the newest advances in methods and tools based on dataflow models, and to give an overview of the state-of-the art in this important area of embedded system design.

Reconfigurable Systems and Tools for Signal and Image Processing
Co-Chairs:

Diana Göhringer, Xilinx, IE
Juanjo Noguera, Xilinx, IE
Sebastien Pillement, U. of Rennes 1, FR
Abstract:
This special session focuses on reconfigurable systems, development tools and runtime managers for signal and image processing applications.  Due to their high degree of parallelism and their flexibility, reconfigurable systems, such as field programmable gate arrays, are an interesting platform for signal and image processing applications. However, the efficient programming of reconfigurable architectures is still difficult. Therefore, high level tools are needed to abstract from the underlying hardware and to leverage the development effort for the user. To optimally exploit the hardware resources at runtime depending on the application requirements, special operating systems are needed.

A further topic is the comparison of reconfigurable systems with other common architectures to evaluate the pros and cons of reconfigurable architectures for signal and image processing applications, it is essential to compare them against other commonly used architectures, such as GPUs or DSPs.

Topics of interest include (but are not limited to):
  • Novel reconfigurable systems and architectures for signal and image processing applications
  • Design tools and frameworks for reconfigurable systems for signal and image processing applications
  • Operating systems and runtime managers for signal and image processing applications
  • Signal and image processing applications on reconfigurable architectures
  • Comparison of reconfigurable systems against other architectures (e.g. GPUs, DSPs) for signal and image processing applications
 
Visual Surveillance
Co-Chairs:
Marek Gorgon, U. of AGH, PL
Walter Stechele, TUM, DE
Abstract:
Due to the need for safety as a major issue in our society, visual surveillance is widely employed today, allowing for perception of humans, objects, and dedicated events. However, some manual observation is necessary and automated techniques still need to be researched. In this special session, the focus will be on realtime techniques for visual surveillance, including motion detection, object recognition, on various levels of abstraction, from image data to higher level feature analysis. Hardware/software optimization techniques for manycore processors, FPGA, GPU, DSP will be presented, with a focus on co-optimization for both hardware and software.

 

DASIP is an event by


DASIP 2012 is organized with the technical co-sponsorship of
IEEE & IEEE Signal Processing Society

   
 

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