Reliable Multi-Processor Scheduling and HW/SW Resource Management

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DASIP 2010
Conference on Design & Architectures for Signal & Image Processing

November 26-28, 2010
Edinburgh, Scotland

Christophe Bobda - University of Potsdam, Germany
David Andrews - University of Arkansas, USA

The last few years have seen pivotal changes in processor architectures. Power consumption and marginal speed-ups from historic instruction level parallelism have motivated the emergence of multicore chip architectures. Performance enhancements for applications will now be provided through multiprocessing approaches on scalable numbers of cores instead of increased clock speeds and dynamic ILP. Moore’s law within the multicore era will continue, but should be interpreted in terms of a doubling of processors instead of transistors. The switch to parallel processing within multicores brings great challenges in programming models and run time systems to support non-uniform memory hierarchies, programmable interconnection networks, and efficient access to shared resources from processors with heterogeneous instruction set architectures. Moreover, chips with reconfigurable hardware raise the possibilities of dynamic adaptation of the system resources to responding to system requirements changes during system operation. Finally, the real-time requirements of embedded systems put yet additional constraints on how parallel applications run and how system resources are allowed. Taken together, all of these new operational requirements are well beyond the capabilities of our current state of the art scheduling theories and algorithms that grew from simple time sharing of a common single processor resource.

The purpose of the session “Reliable Multi-Processor Scheduling and HW/SW Resource Management” is to bring researchers working in the field of Multiprocessing on Chip together to present and discuss their contribution in this rapidly evolving area. Attendees should be provided a big picture in this quickly expanding field with the focus on the management of resources on multiprocessor on chip.

Field of Interest
Fields of interest for this session are but not limited to:

  • Global scheduling for heterogeneous multiprocessor on chip
  • Scheduling and temporal placement
  • Task preemption and relocation techniques
  • Task mapping  under communication constraint and side effect like cache corruption and lock preemption
  • Benchmarking and performance studies
  • Operating Systems for On-Chip Multiprocessor
  • Tool support for Hardware design of On-Chip Multiprocessor
  • Architecture support
  • Scheduling under real-time constraint Communication protocols


Authors are encouraged to submit their paper under the DASIP submission page with a reference to this session. Submitted manuscripts must not have been published previously nor be under consideration for publication elsewhere. Moreover, submission to this session will be deemed to imply that the manuscript will not be submitted elsewhere if accepted.
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