Call for Contributions - Special Sessions

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DASIP 2009

Conference on Design & Architectures for Signal & Image Processing

October 22-24, 2009
Sophia Antipolis, France


A number of special sessions are planned during the Conference. We have two special sessions approved so far. If you wish to propose a special session you can still do so by submitting the following via e-mail (in either pdf or plain ascii text form) to Ahmet [dot] Erdogan [at] ee [dot] ed [dot] ac [dot] uk.

  • Title of the proposed special session

  • Rationale of the need for the special session at DASIP 2009

  • Short biography of the special session organizers

If you want to contribute to any of the special sessions approved so far (please see below) you should submit your paper via the online submission link.
Papers should conform to the formatting and electronic submission guidelines of a regular DASIP paper.

Accepted sessions so far:

Reconfigurable Video Coding- Scheduling and Dynamic Reconfiguration of Dataflow Programs
Multimedia coding technology, after about 20 years of active research, has delivered a rich variety of different and complex coding algorithms.
Selecting an appropriate subset of these algorithms would, in principle, enable a codec designer to produce any desired trade-off between compression performance and implementation complexity.
Currently, interoperability demands that this selection process be "hard-wired'' into the normative description of the codec, or at best, a number of choices codified within the media syntax (i.e. MPEG profiles). To fill this requirement, an important research effort is currently undertaken by ISO/IEC MPEG committee in the project called Reconfigurable Video Coding (RVC).
The final objective of RVC approach is to enable arbitrary combinations of fundamental video coding algorithms to be assembled, without additional standardization steps, because everything necessary for decoding is delivered alongside the content itself. The side-information can consists of a description of the content syntax, as well as a description of the decoder configuration. Decoder configuration information is provided as a description of the interconnections between algorithmic blocks. The approach is based on describing all “algorithms” under the form of “library” of coding algorithms using the data flow programming language.
This special session focuses on dataflow as a practical programming methodology for reconfigurable, parallel and heterogeneous platforms. Dataflow as a design methodology for concurrent and reconfigurable systems has a long tradition, especially in the context of digital signal processing (DSP).
The emphasis in this session will be on the scheduling, matching and dynamic reconfiguration of RVC dataflow programs.

Biography of Mickaël Raulet:
Mickaël Raulet received his postgraduate certificate in signal, telecommunications, images, and radar sciences from Rennes University in 2002, and his Engineering degree in electronic and computer engineering from National Institute of Applied Sciences (INSA), Rennes Scientific and Technical University. In 2006, he received a Ph.D. degree from INSA in electronics and signal processing in collaboration with the software radio team of Mitsubishi Electric ITE (Rennes –France). He is currently in the Institute of Electronics and Telecommunications of Rennes (IETR) where he is a research engineer in rapid prototyping of standard video compression on embedded architectures (multi DSP architectures). Since 2007, he is involved in the ISO/IEC JTC1/SC29/WG11 standardization activities (better known as MPEG) as a Reconfigurable Video Coding Expert. His interests include video standard compression and telecommunication algorithms and rapid prototyping on multi-DSP architectures from Texas Instruments.

Biography of Jean-Francois Nezan:
Jean-Francois Nezan is an Assistant Professor at National Institute of Applied Sciences of Rennes (INSA) and a member of the IETR laboratory in Rennes. He received his postgraduate certificate in signal, telecommunications, images, and radar sciences from Rennes University in 1999, and his engineering degree in electronic and computer engineering from INSA-Rennes Scientific and Technical University in 1999. He received his Ph.D. degree in electronics in 2002 from the INSA. His main research interests include image compression algorithms and multi-DSP rapid prototyping.

Preliminary List of Invited Submissions:

Title: "Scheduling and reconfiguration in Canals and CAL"
Authors: Andreas Dahlin, Johan Ersfolk, Haitham Habli, Guifu Yang, Johan Lilius
Affiliations: Center for Reliable Software Technology Åbo Akademi University

Abstract: Recently CAL has been proposed as an approach to describe Reconfigurable Video Codecs. Independently of this we have developed a language Canals, whose aim is to allow for the fine-grained control of the computation schedules. In this talk we will discuss how to use Canals to model Reconfigurable Video Codecs, and contrast this with the CAL approach. We will close with some discussion about some possibilities for integration of the approaches.

Title: Algorithm / Architecture co-exploration of dataflow models for multicore architecture
Jani Boutellier, Victor Martin-Gomez, Christophe Lucarz and Olli Silven
Affiliations: University of Oulu, EPFL
Abstract: The new model of computation (MoC) used to specify video coding tools algorithms in MPEG in the new standard Reconfigurable Video Coding (RVC) marks a transition in the way video algorithms are specified. The imperative and monolithic reference software are replaced by a collection of inter-connected and concurrent Functional Units. Different connections between the FUs lead to different decoders, each having its own characteristics. All previous standards (MPEG-2 MP, MPEG-4 SP, AVC, SVC…) can be built within RVC. But the problem arises at the implementation step of these decoder models. The models are not always adapted to the architecture on which they are going to be implemented and performances may not always be satisfactory. Thus, some modifications in the structure of these models are necessary in order to obtain better performances. CAL language is well adapted for describing highly concurrent algorithms system but the level of parallelism shown in the CAL model is crucial when implementing them on multiprocessor platforms. CAL is a high level and dataflow/actor based language which enables designers to modify quickly the models. First, the paper shows that the Permutated Flow Shop scheduling problem helps in determining the assignments of actions to processors. Then, the paper shows that by making the model adapted to the underlying architecture, the implemented CAL model gains in performances.

Title: A Fully Re-configurable Universal Video Decoder
Authors: Iain E Richardson, Chaminda S Kannangara, Maja Bystrom, Manuel de Frutos Lopez; James Philp
Affiliations: The Robert Gordon University, Boston University, Universidad Carlos III de Madrid
Abstract: Fully Configurable Video Coding is a new approach to video codec implementation that builds on the strengths of MPEG RVC and adaptive video coding techniques. A common decoding engine, the Universal Video Decoder (UVD), can be configured to decode any video sequence or syntax. The encoder sends a set of configuration commands which define a video decoding process in terms of a set of primitive operations and interconnections. The UVD generates and connects new functional processing units according to these commands and can then proceed to decode a particular video syntax. In this paper we describe a prototype UVD implemented in C++ software. The prototype UVD can be configured and re-configured dynamically (i.e.
during a communication session) and is capable of real time video decoding. Configuration and re-configuration of the UVD is achieved by sending decoding functions, replacing existing functions, for example, replacing one transform with another, or creating new functions which are linked in to the current decoder structure. The UVD receives these configuration commands and creates corresponding C++ objects to implement the required decoding functions. Video is then decoded by stepping through these C++ objects. This paper describes the prototype UVD, explains the process of dynamic re-configuration and presents performance results on a PC platform.

Title: Scheduling and code generation of the Interface-based SDF hierarchy
Authors: Jonathan Piat, Shuvra S. Bhattacharyya, Mickaël Raulet and Maxime Pelcat
Affiliations: IETR/INSA of Rennes, University of Maryland
Abstract: Dataflow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new hierarchy semantic based on interfaces that fixes the number of tokens consumed/produced by a hierarchical vertex has been proposed in order to extend the expressive power of the basic model. This interface-based hierarchy gives the application designer more flexibility to have an iterative approach, and to make optimized choices a the designing level. In this paper we present the scheduling of this special hierarchy type and its efficient C code generation.

Title: An Iterative Methodology for Efficient Implementation of RVC VTL FUs: An MPEG RVC AVC Baseline Encoder Case Study
Authors: Hussein Aman-Allah, Ehab Hanna, Karim Maarouf, and Ihab Amer
Affiliations: Laboratory of Microelectronic Systems (GR-LSM), EPFL
Abstract: Efficient implementations of multimedia algorithms need to exploit the resources and the flexibility of the reconfigurable architectures featured by the newer generations of platforms. Such platforms are characterized by multicore parallel architectures with ever increasing processing capabilities. Classical development methods have failed to fully capture the potential exhibited by such advancements in architecture and hence the corresponding development methodologies need to evolve as well. This paper describes a new methodology for efficient implementations of RVC compliant video coding tools. The methodology introduces an iterative design flow aiming at algorithm and architecture co-exploration starting by an RVC-CAL description that gradually evolves into a possibly mixed SW and HW implementation. The proposed methodology follows an iteration-based implementation model rather than the traditional sequential model. A case study is conducted to illustrate the productivity of the proposed methodology in which the implementation of an AVC baseline encoder. The encoder has been partitioned into several modules trying to maximize the commonality of each component and thus the reconfigurability and reusability for different standards and profiles. This makes the described components potential elements of the encoder VTL of the RVC standard.

Title: Scheduling of CAL models by extending the Flow Shop scheduling problem
Authors: C. Lucarz, A. Dahlin
Affiliations: Laboratory of Microelectronic Systems (GR-LSM), EPFL
Abstract: The new model of computation (MoC) used to specify video coding tools algorithms in MPEG in the new standard Reconfigurable Video Coding (RVC) marks a transition in the way video algorithms are specified. The imperative and monolithic reference software are replaced by a collection of inter-connected and concurrent Functional Units. Different connections between the FUs lead to different decoders, each having its own characteristics. All previous standards (MPEG-2 MP, MPEG-4 SP, AVC, SVC…) can be built within RVC. But the problem arises at the implementation step of these decoder models, especially on the scheduling aspect. In Synchronous Dataflow graph, represented as Directed Acyclic Graphs (DAG), the dependencies between the actions do not change. Every execution of the algorithm follows this DAG. But in CAL models, more dynamism is allowed. It means that the order of execution of the actions depends on the value of the tokens. This makes the implementation of the CAL models even harder. The Permutated Flow Shop scheduling problem helps in determining the scheduling of the actions of the CAL models on a given set of targets (processors, FPGA, DSPs…). This paper shows that we can extend the Flow Shop scheduling problem in order to take under account this dynamism and in order to find a scheduling of the actions on the processors that optimize a given criteria, for example throughput. Integer Linear Programming is used in order to solve this combinatorial problem.

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