Prelimary Program

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DASIP 2016
Conference on Design & Architectures for Signal & Image Processing
October 12-14, 2016
Rennes, France

 
 


ALTERA Workshop : OpenCL ALTERA flow workshop

It is a one day hands-on training being held on Tuesday October 11, 2016, from 9:00 am to 5:00 pm.
Details of the workshop here
 

Wednesday, October 12

08:15 - 09:00 Registration
09:00 - 09:30     Opening Session
09:30 - 10:30    Keynote 1 : Dr Andrew EnsorAuckland University of Technology, NZ
Designing the Square Kilometre Array Computer System
10:30 - 11:00    Coffee Break
11:00 - 12:40 Session 1 : HEVC in Embedded Systems
Chair : Eduardo Juarez, UPM
12:40 - 14:00   Lunch
14:00 - 15:40   Session 2 : Architectures for Image Processing
Chair : Francesca Palumbo, University of Sassari
15:40 - 16:10 Coffee break
16:10 - 17:50 Session 3 : Method and Tools for System Design
Chair : Diana Goehringer, University of Bochum
19:00 - 21:30   Demo Night

 

Thursday, October 13

08:40 - 09:40 Keynote 2 : Sébastien Le Beux, Ecole Centrale de Lyon, FR
Enlightening Many-Core Architectures with Silicon Photonic Interconnects
09-40 - 09:55    Coffee Break
09:55 - 12:00 Special Session 1: Automotive Parallel Computing Challenges – Architectures, Applications, and Tricks 
Chair : Walter Stechele, TUM
12:00 - 12:45  Lunch
12:45 - 14:00  Session 4: Application Specific Hardware Architectures
Chair : Morteza Biglari-Abhari, University of Auckland
14:00 - 14:15  Coffee Break
14:30 - 22:00   Social Event

 

Friday, October 14

09:00 - 10:00    Keynote 3 : Jaan Raik, Tallinn University of Technology, EST
Towards Cost-effective, Resilient Many-core Architectures
10:00 - 11:00    Coffee Break & Poster Session
11:00 - 12:15   Special Session 2: Computer Vision and Image Analysis
Chair : Patrice Delmas, University of Auckland
12:15 - 14:00 Lunch
14:00 - 15:40 Session 5: Image Processing on Multicore Plateforms
Chair : Pierre Langlois, Polytechnique Montreal
15:40 - 16:00  Closing Session

Wednesday October 12:
Keynote :
Designing the Square Kilometre Array Computer System
Dr Andrew EnsorAuckland University of Technology, NZ

Abstract :
The Square Kilometre Array Project is the largest mega-science project of the next decade. It presents numerous computing challenges, particularly in its central signal processor that will process terabytes of incoming data every second, and in its science data processor with Exascale compute requirements. This talk will outline the Project’s signal and image processing pipelines and some designs that seek to overcome the limitations of current technologies.
 
Session 1 : HEVC in Embedded Systems
Efficient Parallel Architecture of an Intra-only Scalable Multi-layer HEVC Encoder
Ronan Parois, Raulet Mickael, Mora Elie Gabriel, Hamidouche Wassim and Deforges Olivier.
 
Scalable HEVC Decoder for Mobile Devices: Trade-offs between Energy Consumption and Quality
Erwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat and Daniel Menard.
 
Estimating Encoding Complexity of a Real-Time Embedded Software HEVC Codec
Alexandre Mercat, Wassim Hamidouche, Maxime Pelcat and Daniel Menard.
 
Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model
Georgios Georgakarakos, Simon Holmbacka and Johan Lilius.

Session 2 : Architectures for Image Processing
ELM-based Hyperspectral Imagery Processor for Onboard Real-time Classification
Koldo Basterretxea, Unai Martinez-Corral, Raul Finker de La Iglesia and Ines Del Campo Hagelstrom.
 
Associative Memory Based on Clustered Neural Networks: Improved Model and Architecture for Oriented Edge Detection
Robin Danilo, Hugues Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia and Philippe Coussy.
 
Memory Efficient Multi-Scale Line Detector Architecture for Retinal Blood Vessel Segmentation
Hamza Bendaoudi, Pierre Langlois and Farida Cheriet.
 
SystemC Modelling of Lossless Compression IP cores for Space Applications
Lucana Santos, Ana Gómez, Pedro Hernandez-Fernandez and Roberto Sarmiento.
 
Session 3 : Method and Tools for System Design
A System-level Security Approach for Heterogeneous MPSoCs
Benjamin Tan, Morteza Biglari-Abhari and Zoran Salcic.
 
Low Power Design Methodology for Signal Processing Systems using Lightweight Dataflow Techniques
Lin Li, Tiziana Fanni, Timo Viitanen, Renjie Xie, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala and Shuvra Bhattacharyya.
 
Code Generation for a SIMD Architecture with Custom Memory Organization
Mehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski and Andreas Karlsson.
 
Fuzzy Logic Modeling for Objective Image Quality Assessment
Ghislain Takam Tchendjou, Rshdee Alhakim and Emmanuel Simeu.
 
Thursday, October 13
Keynote :
Enlightening Many-Core Architectures with Silicon Photonic Interconnects
Sébastien Le Beux, Ecole Centrale de Lyon, FR

Abstract :
The shift to very high performance distributed Many-Cores Systems-on-Chip as mainstream computing devices is the recognized route to address, in particular, power issues by reducing individual processor frequency while retaining the same overall computing power. However, the move to such architectures requires organized high-speed communication between processors and therefore has an impact on the interconnect structure. It clearly relies upon the existence of an extremely fast and flexible interconnect architecture, to such a point that the management of communication between processors is a key to successful improvement. Silicon photonic interconnects are emerging as potential contenders to solve congestion and latency issues in future computing architectures. In this talk, I will firstly present the constituent elements of a basic integrated optical interconnect link and associated technology and design issues. I will then cover comparisons between existing interconnect solutions, including wavelength-routed interconnect and dense wavelength division multiplexing channels. Novel disruptive design methods to solve the thermal sensitivity issues of silicon photonics interconnects will then be introduced. 
 
Special Session 1: Automotive Parallel Computing Challenges – Architectures, Applications, and Tricks 
Monte Carlo Method Based Precision Analysis of Deep Convolution Nets
Robert Krutsch and Sharath Subramanya Naidu.
 
Hardware Acceleration of Maximum-Likelihood Angle Estimation for Automotive MIMO Radars
Frank Meinl, Martin Kunert and Holger Blume.
 
FPGA memory optimization for real-time imaging
Dominique Houzet, Virginie Fresse and Hubert Konik.
 
FPGA-Based Hardware-in-the-Loop Environment Using Video Injection Concept for Camera-Based Systems in Automotive Applications
Mateusz Komorkiewicz, Krzysztof Turek, Pawel Skruch, Tomasz Kryjak and Marek Gorgon.
 
Generation of Schedule Tables on Multi-core Systems for AUTOSAR Applications
Wenhao Wang, Benoît Miramond and Fabrice Camut.

Session 4: Application Specific Hardware Architectures
Hardware Architecture for Lowering the Error Floor of LTE Turbo Codes
Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jego, Benjamin Gadat and Nicolas Van Wambeke.
 
ARM-FPGA Based Platform for Automated Adaptive Wireless Communication Systems Using Partial Reconfiguration Technique
Mohamad Alfadl Rihani, Jean-Christophe Prévotet, Fabienne Nouvel, Mohamad Mroue and Yasser Mohanna
 
Crosstalk-aware Link Power Model for Networks-on-Chip
Erwan Moréac, Andre Rossi, Johann Laurent and Pierre Bomel.

Friday, October 14
Keynote :
Towards Cost-effective, Resilient Many-core Architectures
Jaan Raik, Tallinn University of Technology, EST

Abstract :
In this talk, the newest developments within the Horizon 2020 Research and Innovation Action IMMORTAL are shared. Many-core and Network-on-Chip (NoC) based architectures typically have redundant and distributed resources for processing, communication, memory, and IO. This inherent hardware redundancy can be utilized in implementing systems that are fault-tolerant and degrade gradually. It has been shown how reconfigurable many-core architectures in combination with run-time resource management software can be used to implement fault-tolerance features.  In IMMORTAL an important next step is taken in combining reconfiguration with detailed health information about the running system. This health information identifies faulty components and also reports on health issues warning about fault expectancy. Whereas the former allows reacting on fault and recovering; the later allows anticipating and reconfiguring before faults occur. On top of fault prediction, the talk will envision new, cost-effective fault-tolerant NoC architectures, where the goal is to avoid losing links between the resources in the case of faults, therefore eliminating the need for costly task migration/remapping procedure.

 

Posters :
Signal Processing Based BioSignal Feature Extraction and Classification Techniques for IoT Healthcare Platform: Survey
Amleset Kelati
 
Virtual Prototyping of Automotive Systems: Towards Multi-level Design Space Exploration
Letitia Li, Ludovic Apvrille and Daniela Genius
 
Multi-agents System for Modular Image Processing
Tifaine Inguere, Florent Carlier and Valérie Renault

Parallelism Exploitation of a Dimensionality Reduction Algorithm Applied to Hyperspectral Images
Raquel Lazcano, Daniel Madroñal, Karol Desnos, Maxime Pelcat, Raúl Guerra, Sebastián López, Eduardo Juárez and César Sanz 

FPGA Implementation for 2D Occupancy Grid Map Reconstruction
Ali Alhamwi and Jonathan Piat 
 
Multi-source Energy Harvesting for IoT nodes
Philip-Dylan Gleonec, Jeremy Ardouin, Matthieu Gautier and Olivier Berder 

Soft Detector Architecture Based on Belief Propagation for MIMO Systems
Ali Haroun, Charbel Abdel Nour, Matthieu Arzel and Christophe Jego

Wavelength Allocation for Efficient Communications on Optical Network-on-Chip
Jiating Luo, Van Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Ian O'Connor and Olivier Sentieys
 
Special Session 2: Computer Vision and Image Analysis
Memory Management in Embedded Vision Systems: Optimization Problematic and Solution Methods
Khadija Hadj Salem, Yann Kieffer and Stéphane Mancini.
 
A Comparison of Cost Construction Methods onto a C6678 Platform for Stereo Matching.
Judicael Menant, Guillaume Gautier, Jean Francois Nezan, Luce Morin and Muriel Pressigout.
 
A Dedicated Lightweight Binocular Stereo System for Real-time Depth-map Generation
Trevor Gee, Patrice Delmas, Sylvain Joly, Valentin Baron, Rachel Ababou and Jean-Francois Nezan.

Session 5: Image Processing on Multicore Plateforms
Batched Cholesky Factorization for Tiny Matrices
Florian Lemaitre and Lionel Lacassagne.
 
Custom Processor Design for Efficient, yet Flexible Lucas-Kanade Optical Flow
Sander Smets, Toon Goedemé and Marian Verhelst.
 
A Pipelined Multi-softcore Approach for the HOG Algorithm
José A. M. De Holanda, João Manuel Paiva Cardoso and Eduardo Marques
 
Hyperspectral Image Classification Using a Parallel Implementation of the Linear SVM on a Massively Parallel Processor Array (MPPA) Platform
Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Gustavo Marrero, Eduardo Juárez and César Sanz
 
Demo Night:
 
GAUT - High-Level Synthesis Tool From C/C++ to RTL
Philippe Coussy, Ghizlane Lebtreton and Jorgiano Vidal
 
Efficient Delay and Apodization for on-FPGA 3D Ultrasound
Ahmet Caner Yüzügüler, William Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran and Giovanni De Micheli
 
How Fuzzy Logic Can Enhance Energy Management in Wireless Sensor Nodes Equipped by Energy Harvesters and Wake-up Radios
Fayçal Ait Aoudia, Matthieu Gautier and Olivier Berder
 
UHD Live Video Streaming with a Real-time Scalable HEVC Encoder
Ronan Parois, Hamidouche Wassim, Mora Elie Gabriel, Mickael Raulet and Olivier Deforges
 
HELICoiD Tool Demonstrator for Real-Time Brain Cancer Detection
Ruben Salvador, Himar Fabelo, Raquel Lazcano, Samuel Ortega, Daniel Madroñal, Gustavo M. Callicó, Eduardo Juarez and Cesar Sanz

4K Real-Time Video Streaming in Hybrid Codec Scalability SHVC Configuration
Pierre-Loup Cabarat, Wassim Hamidouche, Olivier Deforges, Mickaël Raulet and Jean Le Feuvre
 
Overlay Architectures for Heterogeneous FPGA Cluster Management
Théotime Bollengier, Loic Lagadec, Mohamad Najem and Jean-Christophe Le Lann
 
Reconfigurable Platform Composer Tool Project
Carlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo, Maxime Pelcat and Francesca Palumb
 
ADAS Demonstration on MPPA Manycore Processor
Pierre-Edouard Beaucamps

Zyggie: Wireless Sensor Node Prototype for Tracking and Gesture Recognition
Antoine Courtay, Mickaël Le Gentil, Olivier Berder and Arnaud Carer

FPGA-based Platform For Real-Time Processing of Electrophysiological Signals: The QRS Segmentation Issue
Mehdi Terosiet, Amina Abiboulah, Aymeric Histace and Olivier Romain

QoS in a Faulty Digital GPS Receiver
Mohamed Mourad Hafidhi, Emmanuel Boutillon and Arnaud Dion

Ker-ONE: Embedded Virtualization Approach with Dynamic Reconfigurable Accelerators Management
Tian Xia, Mohamad Alfadl Rihani, Jean-Christophe Prevotet and Fabienne Nouvel

SLP-aware Word Length Optimization
Ali Hasssan El Moussawi and Steven Derrien

FPGA-based Implementation of a Flexible FFT Dedicated to LTE Standard
Mai-Thanh Tran, Emmanuel Casseau and Matthieu Gautier

FPGA Implementation of the Flux Tensor Moving Object Detection Method - a Demonstration
Piotr Janus, Kamil Piszczek, Tomasz Kryjak and Marek Gorgon

An Embedded Vision System Supporting the Home Care for Convalescent or Elderly People
Piotr Konopka, Tomasz Jonak, Tomasz Kryjak and Marek Gorgon

Accurate Modeling of Fault Impact in Arithmetic Circuits
Pierre Guilloux and Arnaud Tisserand

FPGA-based Bio-inspired Architecture for Multi-scale Attentional Vision
Nicolas Cuperlier, Frédéric Demelo and Benoit Miramond

Autonomous Vehicle Model with Vision-based Tracking System
Krzysztof Mazur, Tomasz Kryjak and Marek Gorgon

A FPGA Platform to Measure Power Consumption
Magali Le Gall and Sylvie Kerouedan

 

 

 
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