Keynotes

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DASIP 2016
Conference on Design & Architectures for Signal & Image Processing
October 12-14, 2016
Rennes, France

 
DASIP 2016 is pleased to welcome Andrew Ensor, Sébastien Le Beux and Jaan Raik as keynotes.
The following topics will be developped during the conference :
 
 
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Designing the Square Kilometre Array Computer System, Dr Andrew Ensor
Abstract :

The Square Kilometre Array Project is the largest mega-science project of the next decade. It presents numerous computing challenges, particularly in its central signal processor that will process terabytes of incoming data every second, and in its science data processor with Exascale compute requirements. This talk will outline the Project’s signal and image processing pipelines and some designs that seek to overcome the limitations of current technologies.
 
Biography:
Dr Andrew Ensor is the Director of the High Performance Computing Research Laboratory at Auckland University of Technology in New Zealand. His research interests include HPC and GPU computing, distributed and mobile system, algorithms, concurrency and computer graphics. Andrew is also the Director of the New Zealand Alliance, a group of over thirty NZ academic and industry partners working on the Exascale computer design for the Square Kilometre Array Project.

 
Enlightening Many-Core Architectures with Silicon Photonic Interconnects, Sébastien Le Beux
Abstract:

The shift to very high performance distributed Many-Cores Systems-on-Chip as mainstream computing devices is the recognized route to address, in particular, power issues by reducing individual processor frequency while retaining the same overall computing power. However, the move to such architectures requires organized high-speed communication between processors and therefore has an impact on the interconnect structure. It clearly relies upon the existence of an extremely fast and flexible interconnect architecture, to such a point that the management of communication between processors is a key to successful improvement. Silicon photonic interconnects are emerging as potential contenders to solve congestion and latency issues in future computing architectures. In this talk, I will firstly present the constituent elements of a basic integrated optical interconnect link and associated technology and design issues. I will then cover comparisons between existing interconnect solutions, including wavelength-routed interconnect and dense wavelength division multiplexing channels. Novel disruptive design methods to solve the thermal sensitivity issues of silicon photonics interconnects will then be introduced. 
 
Biography:
Sébastien Le Beux is Associate Professor for Heterogeneous and Nanoelectronics Systems Design at Ecole Centrale de Lyon. He is currently responsible for nanoprocessors research activities at the Heterogeneous System Design group of the Lyon Institute of Nanotechnology. He obtained his PhD in Computer Science from the University of Sciences and Technology of Lille in 2007. He went on to become a postdoctoral researcher at Ecole Polytechnique de Montréal, Canada 2008-2010. In 2013, he was invited to the University of Science and Technology Hong Kong as visiting scholar. His research interests include design methods for emerging (nano)technologies and embedded systems, including silicon photonic interconnect and reconfigurable architectures. He has authored or co-authored over 70 scientific publications including journal articles, book chapters, patent and conference papers and held pivotal positions in the organization of various international conferences. He is a general chair of the OPTICS workshop.
 
Torwards cost-effective, resilient many-core architectures, Jaan Raik
Abstract:

In this talk, the newest developments within the Horizon 2020 Research and Innovation Action IMMORTAL are shared. Many-core and Network-on-Chip (NoC) based architectures typically have redundant and distributed resources for processing, communication, memory, and IO. This inherent hardware redundancy can be utilized in implementing systems that are fault-tolerant and degrade gradually. It has been shown how reconfigurable many-core architectures in combination with run-time resource management software can be used to implement fault-tolerance features.  In IMMORTAL an important next step is taken in combining reconfiguration with detailed health information about the running system. This health information identifies faulty components and also reports on health issues warning about fault expectancy. Whereas the former allows reacting on fault and recovering; the later allows anticipating and reconfiguring before faults occur. On top of fault prediction, the talk will envision new, cost-effective fault-tolerant NoC architectures, where the goal is to avoid losing links between the resources in the case of faults, therefore eliminating the need for costly task migration/remapping procedure.
 
Biography:
Jaan Raik is a Professor at the Department of Computer Engineering of Tallinn University of Technology. His research interests include test, verification and fault tolerant design of computing systems. He is a member of IEEE Computer Society and HiPEAC, a member of steering/program committees of several conferences and has co-authored more than 200 scientific publications. He is the General Chair of the IFIP/IEEE VLSI-SoC’16 Conference and the Program Co-Chair of CDN-Live’16. He also served as the General Chair of IEEE DDECS’12 and the Program Chair of IEEE DDECS’15. He is currently coordinating the Horizon 2020 RIA IMMORTAL from ICT-1-Cyber-Physical Systems Call and the Horizon 2020 Twinning project TUTORIAL. 
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