DATE 2013 Tutorial: Advanced Techniques for Power-Aware System-Level Prototyping
DATE 2013 Monday Tutorial
Advanced Techniques for Power-Aware System-Level Prototyping
18 March 2013, 09:00-18:00
Alpexpo Espace, Alpes Congres, Grenoble, France
Announcement at conference website:
Registration (Tutorial B)
In the design of embedded systems extra-functional properties like timing and power need to be considered during the entire design process. Often these properties can only be estimated after manually implementing a design for a certain target platform and using component-level timing and power analysis tools. At the same time, exploration, analysis, and optimization of embedded applications running on today’s platforms require fast and early virtual system models enabling the consideration of extra-functional properties under real-world application scenarios.
With a group of experts from industry and academia, the tutorial discusses the major challenges and presents novel and innovative research results including tool support to create timing and power-aware Virtual Platforms. In this context, the following key aspects are covered:
- Model-driven design and automatic platform performance and power model synthesis, enabling early design space exploration
- Efficient application mapping onto resource-constrained platform models
- Early and automatic timing and power estimation for embedded software and custom hardware components, suitable for integration into Virtual Platform models
- RTL-to-TLM re-synthesis and abstraction of timing and power properties, suitable for integration into Virtual Platform models
The presentations will be accompanied by concrete tool introductions and demonstrations, showing how the presented concepts support improvement of today’s state-of-the-art system-level design flows.
Power consumption is the limiting physical factor of many current and future systems, especially in the growing mobile computing market.
Consequently, successfully mastering the trade-offs between performance and power efficiency is required for future innovative and competitive products. The presented results have been developed in a series of collaborative European research projects and have been integrated into a holistic reference design flow during the COMPLEX project, to be completed in March 2013. During the last phase of this project a wide set of methods and tools have been applied successfully in different domains in mobile computing: Healthcare, Space, Security, and mobile communication. In a full-day tutorial, the COMPLEX reference framework, including industrial experience reports and the integration of latest findings into commercial tools, will be presented in a consistent way.
Participants will take a broad knowledge of today’s state-of-the-art concepts, key technologies, and tools for efficient application mapping; platform exploration, selection and configuration based on Virtual Platforms; as well as static and dynamic abstraction, estimation and analysis methods for system-level models including extra-functional properties like power consumption. This enables the attendees to adopt new concepts in competitive industrial R&D or to explore future directions of academic research.
The tutorial is targeted towards academic researchers and industrial practitioners concerned with system-level design and exploration of embedded applications efficiently running on heterogeneous, power-constrained multicore architectures. At a broader scale, it will be of interest to the majority of DATE attendees working on Embedded System Design in general.
0930 – 1100
Introduction and tutorial overview
Frank Oppenheimer, OFFIS
An MDD Methodology for Specification and Performance Estimation of Embedded Systems
Eugenio Villar, UC
1100 – 1130 Break
1130 – 1300
Virtual Platform Generation, Integration and Extension of Extra-Functional Properties
Tesnim Abdellatif, MDS
Industrial experience report for model-based design in space/aerospace applications (demo)
Raúl Valencia, GMV
1300 – 1430 Lunch Break
1430 – 1600
From RTL IP to Functional System-Level Models with Extra-Functional Properties
Davide Quaglia, EDAlab
High-Level Synthesis-based Hardware Power and Timing Estimation
Philipp A. Hartmann, OFFIS
1600 – 1630 Break
1630 – 1800
Software Power and Timing Estimation
Carlo Brandolese, PoliMi
Network-aware Design-Space Exploration of a Power-Efficient Embedded Application (demo)
Sara Bocchio, ST-I
Summary and Closing remarks
Frank Oppenheimer, OFFIS
Frank Oppenheimer (OFFIS)
Frank Oppenheimer received his Diploma in 1997 and 2005 his PhD in Computing Science from the Carl v. Ossietzky University Oldenburg where he worked as researcher until 2001. In late 2001 he became Manager of the System Design Methodology Group and in 2008 Director in the R&D division Transportation at the OFFIS Institute for Information Technology. From 2005 until 2010 he was Chair of the LBSD (Language Bases System Design) thematic area of the FDL conference and is reviewing member for the D1 topic at DATE and several other program committees. He is author/coauthor of more than 40 scientific publications and talks. In 2011 he was General Chair of the MBMV workshop and the FDL conference. Frank's long term interests in research are hardware/software interface modeling, programming models for multicore/multiprocessor platforms and synthesis and design methods for heterogeneous, adaptive systems. (back to program)
Eugenio Villar (UC)
Eugenio Villar received the Ph.D. in Sciences (Electronics) in 1984. Since 1992 is Full Professor at the Electronics Technology, Automatics and Systems Engineering Department of the University of Cantabria (ES). He is the responsible of the HW/SW Embedded Systems Design activities inside the Microelectronics Engineering Group of the Department. He is author of more than 100 papers in international conferences, journals and books in the area of specialization and design of electronic systems. His current research interests cover system specification, performance estimation and system synthesis and verification using UML/MARTE and SystemC. These activities are being funded by several FP7, Catrene, Artemis and national and industrial projects. (back to program)
Philipp A. Hartmann (OFFIS)
Philipp A. Hartmann received his diploma in Computer Science from the University of Bonn (DE) in 2006. Since then, he is working in the Hardware/Software Design Methodology (HDM) group at OFFIS Institute for Information Technology in Oldenburg (DE). Currently, he is the technical project manager of the FP7 Integrated Project COMPLEX, coordinated by OFFIS. Since 2009, he is contributing member of several Accellera SystemC working groups and the IEEE P1666 WG, actively participating in the evolution of the corresponding standards and proof-of-concept implementations. His current research interests mainly cover efficient modeling, simulation, analysis and validation of heterogeneous HW/SW systems based on SystemC with and beyond transaction-level models. (back to program)
Adam Moraviec (ECSI)
Adam Morawiec received his MSc degree in electronic system design in 1993 from the Silesian Technical University in Gliwice, Poland and his DEA (Diplome d'Etudes Approfondies) in 1996 and PhD in 2000 in Microelectronics at the TIMA Laboratory / Université Joseph Fourrier, Grenoble, France in the domain of verification and simulation performance methods.
He works for ECSI in the R&D project development and management in the domain of system design methods and standards, in setting up industry and research consortia, in organisation of advanced training and workshop in system design area. He also acted as an expert of the European Commission in the R&D project proposal evaluation and IST/ICT Work programmes definition. Since 2005 he is the director of ECSI.
He is an author of several scientific publications in the area of formal verification, formal models, simulation performance and system design. He is also an editor of two technical books published by Springer Publishers: “Platform Based Design at the Electronic System Level” and “High-Level Synthesis”. (back to program)
Davide Quaglia (EDAlab)
Davide Quaglia received his PhD in Computer Engineering from Politecnico di Torino (IT) in 2003. Currently he is Assistant Professor at the Computer Science Department of the University of Verona (IT) where he currently teaches “HW Architectures for Bioinformatics” and “Design of Networked Embedded Systems”. He is author/co-author of about 50 papers and member of IEEE. He is Chair of the Special Session on Cyber-Physical Systems of Euromicro DSD conference and member of Euromicro DSD as well as ECSI FDL Program Committees. His current research interests include Networked Embedded Systems, Networked Control Systems, Cyber-Physical Systems. He is currently involved in three FP7 European projects, i.e., COMPLEX, SMAC, and TOUCHMORE. He is also co-founder and active project leader of EDALab s.r.l., a spin-off company of the University of Verona. (back to program)
Tesnim Abdellatif (MDS)
Tesnim Abdellatif holds a Ph.D in computer science from Grenoble University, France. Her thesis work at Verimag laboratory included defining rigorous design and implementation methods to ensure correct implementation of real-time systems. Based on formal methods solution, she has conducted successful experiments for robotics systems development in a joined work with the LAAS Laboratory in Toulouse, France. In 2012, she joined Magillem Design Services as a research engineer. She is now working on abstract modelisation of hardware platforms based on IP-XACT descriptions. She is also involved in projects on SW/HW codesign in embedded systems and safety certification of systems software. (back to program)
Carlo Brandolese (PoliMi)
Carlo Brandolese received the degree in electronic engineering in 1995 from the Politecnico di Milano (IT). He worked until 1997 at Central R&D Labs of the Italian telecom company Italtel as CAD engineer, in which position he was responsible for FPGA design flows and methdologies. In 1998, he received the MS degree in information technology from Cefriel (Politecnico di Milano) working on system-level design and codesign issues. Finally, in 2001, he received the PhD degree in information technology and design automation from the Politecnico di Milano with a dissertation on the analysis and optimization of power consumption of heterogeneous embedded system. Since 1998, he has been a consultant at Cefriel in the Embedded System Design Unit and, since 2003, he has been an assistant professor at the Politecnico di Milano. His current interests range from low-power design, software power analysis and optimization, system-level design methodologies, and codesign. (back to program)
Sara Bocchio (ST-I)
Sara Bocchio received the master degree in Electronics Engineering from University degli Studi di Brescia in 1998. Sara has been working in STMicroelectronics since 1999. In 2001 she joined the Advanced System Technologies (AST) department; in 2008 she joined the “Ultra Low Power Platform” group, where she leads the verification activities and she was also involved in the validation and system modeling of ultra-low power SoCs and IPs. She participated to different European projects (among them, the MORPHEUS FP6 project, the MULTI3 FP7 project, and currently the ARTEMIS ASAM and FP7 COMPLEX projects). (back to program)
Raúl Valencia (GMV AD)
Raúl Valencia received his Master of Science degree in Computers engineering degree from the Polytechnic University of Madrid (UPM). Mr. Valencia is a GMV project engineer that has participated in MDE technologies related projects (EU-FP7's COMPLEX project, ESA's OBCP-BB project) mostly centred in analysis and design of HW/SW real-time systems. His experience includes the design of embedded real-time systems using UML's MARTE profile and the development of Eclipse based tools supporting MDE methodologies. (back to program)