COMPLEX

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OBJECTIVES


The primary objective of COMPLEX is to develop an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of embedded HW/SW systems. Complex will focus on early, fast yet accurate platform-based design space exploration at the system level.

The COMPLEX consortium develops a new design environment for platform-based design-space exploration offering developers of next-generation mobile embedded systems a highly efficient design methodology and tool chain. The integrated environment allows iterative exploration and refinement of advanced applications to meet market requirements. The design technology in particular enables fast simulation and assessment of the platform at Electronic System Level (ESL) with up to bus-cycle accuracy at the earliest instant in the design cycle. The main objectives are:

  • Highly efficient and productive design methodology and holistic framework for design space exploration of embedded HW/SW systems. The resulting framework will be platform vendor and application domain independent, provide open interfaces for a later integration of new industry players.

  • Combination and augmentation of well established ESL synthesis & analysis tools into a seamless design flow enabling performance & power aware virtual prototyping from a combined HW/SW perspective

  • Interfacing next-generation model-driven SW design approach and industry standard model-based design environments.

  • Multi-objective co-exploration for assessing design quality and to optimize the system platform with respect to performance, power, and reliability metrics.

  • Fast simulation and assessment of the platform at ESL with up to bus-cycle accuracy at the earliest instant in the design cycle.

  • Optimization benefits from run-time mode adaptation techniques, such as dynamic power management or application adaptation to varying workloads.
     


TECHNICAL APPROACH


Several well established ESL synthesis and analysis tools from vendors such as CoWare, ChipVision, EDALab, and Magillem will be augmented and combined into a seamless design flow enabling performance and power aware virtual prototyping from a combined hardware-software perspective.

For co-development the COMPLEX framework follows a new approach enabling a unified internal representation of the HW and SW world, called basic block & communication accurate (BAC++) technique. BAC++ can be generated by SW cross-compilers and HW behavioural synthesis tools. In the COMPLEX framework, the BAC++ code is integrated into a fast SystemC™/TLM2 virtual platform model, enabling fast system simulation.

The hardware/software co-exploration considers both the architecture design space and the application space to assess trade-offs when co-designing next-generation mobile embedded systems. The co-exploration is multi-objective assess the design quality and to optimize the system platform with respect to performance, power, reliability metrics, etc. The optimization benefits from run-time mode adaption techniques, such as dynamic power management or application adaption to evolving workloads, can be maximised and reported to successive synthesis steps using standardized output formats.

The framework combines several industrial standards for system modelling and integration: Possible design entry is either a MARTE/UML model, offering seamless integration into a model-driven SW design approach or directly C++/SystemC. Then, the IP-XACT platform specification and the BAC++ based SW and dedicated HW descriptions are transformed into a SystemC/TLM2 virtual prototype.
 



 


KEY ISSUES


Existing barriers between HW and SW developers are lowered, allowing SW designers to take more influence on the exploration of the HW platform hiding irrelevant technical details, thus enabling a clear view on the results of the application code transformations in terms of timing behaviour and power consumption.

The COMPLEX framework enables system integrators to find the ideal technology platform. Therefore, it solves the problem of designing embedded systems which are efficient; both in terms of platform resources and power consumption. Technology providers benefit from the COMPLEX results since they can now offer fast but accurate platform models to their customers. EDA companies are gaining from added value through point-tool integration in the COMPLEX framework.
 


EXPECTED IMPACT


The COMPLEX results are expected to support the overcoming of technology roadblocks by reinforcing Europe's industrial strengths for building increasingly smaller, cheaper, more reliable and less power consuming electronic components and systems, taking into account the alternative paths to next generation technologies and sustainable development.

This is a key factor in revolutionizing different applications in health, safety and security, transport, and provision of environmentally friendly sustainable applications. Moreover, this will support the competitiveness of industrial strongholds such as automotive, avionics, industrial automation, consumer electronics, telecoms, and medical systems. Consequently, COMPLEX will be the foundations for innovation in all major products and services.
 


Keywords
 Design Methodology, Electronic System-Level, Design Space Exploration, Timing, Power Consumption, Platform-based Design, Virtual Platform, UML, MARTE, SystemC™, TLM, IP-XACT 

Project Coordinator
Name: Wolfgang Nebel
Institution: OFFIS e.V.
Email: wolfgang [dot] nebel [at] offis [dot] de
 
Project Technical Manager
Name: Kim Grüttner
Institution: OFFIS e.V.
Email: kim [dot] gruettner [at] offis [dot] de
 
Project website: http://complex.offis.de
 
Partners: OFFIS (DE), STMicroelectronics (IT), STMicroelectronics (CN), NXP (NL), Thales Communications (FR), GMV (ES), CoWare (BE), ChipVision (DE), EDALab (IT), Magillem (FR), Politecnico di Milano (IT), Universidad de Cantabria (ES), Politecnico di Torino (IT), IMEC (BE), ECSI (FR)
 
Duration: 36 Months
Start: 2009.12.01
Total Cost: 7.2 M
EC Contribution: 4.8 M
 
Contract Number: IP 247999

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