System Specification and Design Languages: Selected Contributions from FDL 2010

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About this book: 

This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010.  FDL is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

  • Covers design verification, automatic synthesis and mechanized debug aids;
  • Includes language-based modeling and design techniques for embedded systems;
  • Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains;
  • Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE).
Selected Contributions: 
FDL 2010
Series: 
Lecture Notes in Electrical Engineering, Vol. 106
Editor: 
Kaźmierski, Tom J.; Morawiec, Adam (Eds.)
Year: 
2012, 2012, XII, 254 p. 127 illus.
ISBN: 
978-1-4614-1426-1
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Table of contents: 

1 Formal Hardware/Software Co-verification of Application
Specific Instruction Set Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Sacha Loitz, Markus Wedler, Dominik Stoffel,
Christian Brehm, Wolfgang Kunz, and NorbertWehn

2 Evaluating Debugging Algorithms from a Qualitative Perspective . . . 21
Alexander Finder and G¨orschwin Fey

3 Mapping of Concurrent Object-Oriented Models
to Extended Real-Time Task Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Matthias B¨uker, Kim Gr¨uttner, Philipp A. Hartmann,
and Ingo Stierand

4 SystemC-A Modelling of Mixed-Technology Systems
with Distributed Behaviour. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chenxu Zhao and Tom J. Ka´zmierski

5 A Framework for Interactive Refinement of Mixed
HW/SW/Analog Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Tobias Kirchner, Nico Bannow, Christian Kerstan,
and Christoph Grimm

6 Bottom-up Verification for CMOS Photonic Linear
Heterogeneous System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Bo Wang, Ian O’Connor, Emmanuel Drouard,
and Lioua Labrak

7 Towards Abstract Analysis Techniques for Range Based
System Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Florian Schupfer,Michael K¨argel, Christoph Grimm,
Markus Olbrich, and Erich Barke

8 Modeling Time-Triggered Architecture Based Real-Time
Systems Using SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Jon Perez, Carlos Fernando Nicolas, Roman Obermaisser,
and Christian El Salloum

9 Towards the Development of a Set of Transaction Level
Models A Feature-Oriented Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Ye Jun, Tan Qingping, and Li Tun

10 Rapid Prototyping of Complex HW/SW Systems using
a Timing and Power Aware ESL Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Kim Gr¨uttner, Kai Hylla, Sven Rosinger, andWolfgang Nebel

11 Towards Accurate Source-Level Annotation of Low-Level
Properties Obtained from Optimized Binary Code. . . . . . . . . . . . . . . . . . . . . 175
Stefan Stattelmann, Alexander Viehl, Oliver Bringmann,
and Wolfgang Rosenstiel

12 Architecture Specifications in Cλ aSH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Jan Kuper, Christiaan Baaij, Matthijs Kooijman,
and Marco Gerards

13 SyReC: A Programming Language for Synthesis
of Reversible Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Robert Wille, Sebastian Offermann, and Rolf Drechsler

14 Logical Time @ Work: Capturing Data Dependencies
and Platform Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Calin Glitia, Julien DeAntoni, and Fr´ed´eric Mallet

15 Formal Support for Untimed MARTE-SystemC Interoperability .. . . 239
Pablo Pe˜nil, Fernando Herrera, and Eugenio Villar

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